Abstract is missing.
- Message from the Conference Chairs - ASAP 2020Dirk Koch, Frank Hannig, Javier Navaridas. [doi]
- A Template-based Framework for Exploring Coarse-Grained Reconfigurable ArchitecturesArtur Podobas, Kentaro Sano, Satoshi Matsuoka. 1-8 [doi]
- Accelerating Radiative Transfer Simulation with GPU-FPGA Cooperative ComputationRyohei Kobayashi, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Makito Abe, Masayuki Umemura. 9-16 [doi]
- Termination detection for fine-grained message-passing architecturesMatthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew Brown. 17-24 [doi]
- Condensing an overload of parallel computing ingredients into a single architecture recipeRiadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku. 25-28 [doi]
- FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet CapturingShuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda, Koyo Nitta. 29-32 [doi]
- FPGA-Accelerated Time Series Mining on Low-Power IoT DevicesSeongyoung Kang, Jinyeong Moon, Sang-Woo Jun. 33-36 [doi]
- Array Aware Training/Pruning: Methods for Efficient Forward Propagation on Array-based Neural Network AcceleratorsKrishna Teja Chitty-Venkata, Arun K. Somani. 37-44 [doi]
- Design Space Exploration for Softmax ImplementationsZhigang Wei, Aman Arora, Pragenesh Patel, Lizy Kurian John. 45-52 [doi]
- Hamamu: Specializing FPGAs for ML Applications by Adding Hard Matrix Multiplier BlocksAman Arora, Zhigang Wei, Lizy K. John. 53-60 [doi]
- Hardware Acceleration of Large Scale GCN InferenceBingyi Zhang, Hanqing Zeng, Viktor K. Prasanna. 61-68 [doi]
- Training Neural Nets using only an Approximate Tableless LNS ALUMark G. Arnold, Ed Chester, Corey Johnson. 69-72 [doi]
- Temporal Motionless Analysis of Video using CNN in MPSoCSomdip Dey, Amit Kumar Singh, Dilip Kumar Prasad, Klaus D. McDonald-Maier. 73-76 [doi]
- An Efficient Convolution Engine based on the À-trous Spatial Pyramid PoolingCristian Sestito, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri. 77-80 [doi]
- Fast and Accurate Training of Ensemble Models with FPGA-based SwitchJiuxi Meng, Ce Guo, Nadeen Gebara, Wayne Luk. 81-84 [doi]
- Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration SystemDawen Xu 0002, Ziyang Zhu, Cheng Liu, Ying Wang, Huawei Li, Lei Zhang, Kwang-Ting Cheng. 85-92 [doi]
- A Parallel-friendly Majority Gate to Accelerate In-memory ComputationJohn Reuben, Stefan Pechmann. 93-100 [doi]
- A System for Generating Non-Uniform Random Variates using Graphene Field-Effect TransistorsNathaniel Joseph Tye, James Timothy Meech, Bilgesu Arif Bilgin, Phillip Stanley-Marbell. 101-108 [doi]
- Efficient FeFET Crossbar Accelerator for Binary Neural NetworksTaha Soliman, Ricardo Olivo, Tobias Kirchner, Cecilia De la Parra, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn. 109-112 [doi]
- A Design Methodology for Post-Moore's Law Accelerators: The Case of a Photonic Neuromorphic ProcessorArmin Mehrabian, Volker J. Sorger, Tarek A. El-Ghazawi. 113-116 [doi]
- Improved Side-Channel Resistance by Dynamic Fault-Injection CountermeasuresJan Richter-Brockmann, Tim Güneysu. 117-124 [doi]
- Architecture Support for FPGA Multi-tenancy in the CloudJoel Mandebi Mbongue, Alex Shuping, Pankaj Bhowmik, Christophe Bobda. 125-132 [doi]
- FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample SortMikhail Asiatici, Damian Maiorano, Paolo Ienne. 133-140 [doi]
- SLATE: Managing Heterogeneous Cloud FunctionsJessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik. 141-148 [doi]
- Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit ArithmeticNuno Neves 0002, Pedro Tomás, Nuno Roma. 149-156 [doi]
- Anytime Floating-Point Addition and Multiplication-Concepts and ImplementationsMarcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich. 157-164 [doi]
- BWOLF: Bit-Width Optimization for Statistical Divergence with -Logarithmic FunctionsQian Xu, Guowei Sun, Gang Qu. 165-172 [doi]
- Efficient Floating-Point Implementation of the Probit Function on FPGAsMioara Joldes, Bogdan Pasca. 173-180 [doi]
- Combining Fixed-Point and SORN Arithmetic in a MIMO BPSK-Symbol Detection ArchitectureMoritz Bärthel, Jochen Rust, Steffen Paul. 181-184 [doi]
- ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow CalculationMohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno. 185-188 [doi]
- Optimizing Grouped Convolutions on Edge DevicesPerry Gibson, José Cano, Jack Turner, Elliot J. Crowley, Michael F. P. O'Boyle, Amos J. Storkey. 189-196 [doi]
- Dynamic Sharing in Multi-accelerators of Neural Networks on an FPGA Edge DeviceHsin-Yu Ting, Tootiya Giyahchi, Ardalan Amiri Sani, Eli Bozorgzadeh. 197-204 [doi]
- A New Hardware Approach to Self-Organizing MapsLeonardo Alves Dias, Maria G. F. Coutinho, Elena Gaura, Marcelo A. C. Fernandes. 205-212 [doi]
- Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia DetectionJohnson Loh, Jianan Wen, Tobias Gemmeke. 213-216 [doi]