Table of Contents

• To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore ClustersLuca Bertaccini, Luca Benini, Francesco Conti 0001. 1-8 [doi]
• Algorithm and Hardware Co-Design for FPGA Acceleration of Hamiltonian Monte Carlo Based No-U-Turn SamplerYu Wang, Peng Li. 9-16 [doi]
• Improving Inference Lifetime of Neuromorphic Systems via Intelligent Synapse MappingShihao Song, Twisha Titirsha, Anup Das 0001. 17-24 [doi]
• A lightweight ISE for ChaCha on RISC-VBen Marshall, Daniel Page, Thinh Hung Pham. 25-32 [doi]
• RFC-HyPGCN: A Runtime Sparse Feature Compress Accelerator for Skeleton-Based GCNs Action Recognition Model with Hybrid PruningDong Wen, Jingfei Jiang, Jinwei Xu, Kang Wang, Tao Xiao, Yang Zhao, Yong Dou. 33-40 [doi]
• Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA ClusterTomohiro Ueno, Atsushi Koshiba, Kentaro Sano. 41-48 [doi]
• Power, Performance and Area Consequences of Multi-Context Support in CGRAsVimal Chacko, Jason Anderson. 49-52 [doi]
• SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUsLukas Sommer, Michael Halkenhäuser, Cristian Axenie, Andreas Koch 0001. 53-56 [doi]
• NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural NetworksGrant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon. 57-60 [doi]
• Edge-disjoint spanning trees in the line graph of hypercubesYu Qian, Baolei Cheng, Jianxi Fan, Yifeng Wang, Ruofan Jiang. 61-64 [doi]
• Customized Instruction on RISC-V for Winograd-Based Convolution AccelerationShihang Wang, Jianghan Zhu, Qi Wang, Can He, Terry Tao Ye. 65-68 [doi]
• Real-Time Super-Resolution System of 4K-Video Based on Deep LearningYanpeng Cao, Chengcheng Wang, Changjun Song, Yongming Tang, He Li. 69-76 [doi]
• An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-designMingshuo Liu, Shiyi Luo, Kevin Han, Bo Yuan 0001, Ronald F. DeMara, Yu Bai 0004. 77-84 [doi]
• Binary Complex Neural Network Acceleration on FPGA : (Invited Paper)Hongwu Peng, Shanglin Zhou, Scott Weitze, Jiaxin Li, Sahidul Islam, Tong Geng, Ang Li, Wei Zhang, Minghu Song, Mimi Xie, Hang Liu, Caiwen Ding. 85-92 [doi]
• How to Reach Real-Time AI on Consumer Devices? Solutions for Programmable and Custom ArchitecturesStylianos I. Venieris, Ioannis Panopoulos, Ilias Leontiadis, Iakovos S. Venieris. 93-100 [doi]
• Talos: A Weighted Speedup-Aware Device Placement of Deep Learning ModelsYuanjia Xu, Heng Wu, Wenbo Zhang 0006, Chen Yang, Yuewen Wu, Heran Gao, Tao Wang. 101-108 [doi]
• Hodgkin-Huxley-Based Neural Simulation with Networks Connecting to Near-Neighbor NeuronsMasashi Ogaki, Yukinori Sato. 109-116 [doi]
• Accelerating Recurrent Neural Networks for Gravitational Wave ExperimentsZhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk. 117-124 [doi]
• Array-Aware Neural Architecture SearchKrishna Teja Chitty-Venkata, Arun K. Somani. 125-132 [doi]
• TwinDNN: A Tale of Two Deep Neural NetworksHyunmin Jeong, Deming Chen. 133-140 [doi]
• Image caption generation method based on an interaction mechanism and scene concept selection moduleLiping Zhang, Qin Lu. 141-148 [doi]
• OpenCGRA: Democratizing Coarse-Grained Reconfigurable ArraysCheng Tan 0002, Nicolas Bohm Agostini, Jeff Zhang, Marco Minutoli, Vito Giovanni Castellana, Chenhao Xie 0001, Tong Geng, Ang Li, Kevin J. Barker, Antonino Tumeo. 149-155 [doi]
• CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper)Jason Helge Anderson, Rami Beidas, Vimal Chacko, Hsuan Hsiao, Xiaoyi Ling, Omar Ragheb, Xinyuan Wang, Tianyi Yu. 156-162 [doi]
• Number Theoretic Transform Architecture suitable to Lattice-based Fully-Homomorphic EncryptionRogério Paludo, Leonel Sousa. 163-170 [doi]
• ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level CacheSukarn Agarwal, Shounak Chakraborty. 171-174 [doi]
• DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based CryptographyXiao Hu, Minghao Li, Jing Tian 0004, Zhongfeng Wang. 175-178 [doi]
• XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel LeakageThinh Hung Pham, Ben Marshall, Alexander Fell, Siew Kei Lam, Daniel Page. 179-186 [doi]
• Memory-aware Efficient Deep Learning Mechanism for IoT DevicesJishnu Banerjee, Sahidul Islam, Wei Wei, Chen Pan, Dakai Zhu, Mimi Xie. 187-194 [doi]
• AERO: Towards Energy-Efficient Autonomous Flight in MAVs Using Approximate ExecutionBen Li, Jingweijia Tan, Kaige Yan. 196-202 [doi]
• A Low Power Branch Prediction for Deep Learning on RISC-V ProcessorMingjian Sun, Yuan Li, Song Chen 0001, Yi Kang. 203-206 [doi]
• Parallel Construction of Independent Spanning Trees on Folded Crossed CubesHuanwen Zhang, Yan Wang, Jianxi Fan, Ruyan Guo. 207-210 [doi]
• Assessing Robustness of Hyperdimensional Computing Against Errors in Associative Memory : (Invited Paper)Sizhe Zhang, Ruixuan Wang, Jeff Jun Zhang, Abbas Rahimi, Xun Jiao. 211-217 [doi]
• Towards Automatic and Agile AI/ML Accelerator Design with End-to-End SynthesisJeff Jun Zhang, Nicolas Bohm Agostini, Shihao Song, Cheng Tan, Ankur Limaye, Vinay Amatya, Joseph B. Manzano, Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Gu-Yeon Wei, David Brooks 0001. 218-225 [doi]
• ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-designYoshiki Fujiwara, Shinya Takamaeda-Yamazaki. 226-233 [doi]
• A Novel Ring-based Small-World NoC for Neuromorphic ProcessorYuchen Qiu, Chao Xiao, LingHui Peng, Junhui Wang, Ziyang Kang, Shiming Li, Lei Wang. 234-241 [doi]
• Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable ArraysXinyuan Wang, Tianyi Yu, Hsuan Hsiao, Jason Helge Anderson. 242-249 [doi]
• An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift RegistersMurad Qasaimeh, Joseph Zambreno, Phillip H. Jones. 250-257 [doi]
• WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAsXinheng Liu, Yao Chen, Cong Hao, Ashutosh Dhar, Deming Chen. 258-265 [doi]
• FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network InferenceEn-Yu Yang, Tianyu Jia, David Brooks 0001, Gu-Yeon Wei. 266-273 [doi]