Table of Contents

• Message from the General Chair DSD 2023Radovan Stojanovic. [doi]
• Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the FutureMaciej J. Ciesielski. [doi]
• Generating CGRA Processing Element Hardware with CGRAgenHans Jakob Damsgaard, Aleksandr Ometov, Jari Nurmi. 1-7 [doi]
• FPGA-Based Real-Time Laser Beam Profiling and Stabilization System for Quantum Simulation ApplicationsStefano Marti, Enis Mustafa, Giacomo Bisson, Pratyush Anand, Philipp Fabritius, Tilman Esslinger, Abdulkadir Akin. 8-15 [doi]
• Implementation of Sobel Edge Detection on DRRA and DiMArch ArchitecturesPudi Dhilleswararao, Rajeev Ryansh, Vamsi Goudu, Srinivas Boppu, Ahmed Hemani. 16-23 [doi]
• Model Based Design of FMCW Radar Processing Systems on FPGA PlatformsHugues Almorin, Bertrand Le Gal, Christophe Jégo, Vincent Kissel. 24-29 [doi]
• Energy-Efficient Use of an Embedded Heterogeneous SoC for the Inference of CNNsAgathe Archet, Nicolas Ventroux, Nicolas Gac, François Orieux. 30-38 [doi]
• Power-of- Two Quantized YOLO Network for Pedestrian Detection with Dynamic Vision SensorDominika Przewlocka-Rus, Tomasz Kryjak. 39-45 [doi]
• Energy Efficient Versatile Video Coding Decoder Using Lightweight Regression ModelsO. Le Gonidec, Miguel Chavarrías, Anup Saha, Gonzalo Rosa, Fernando Pescador. 46-52 [doi]
• Energy Profiling of DNN AcceleratorsMatthias Wess, Dominik Dallinger, Daniel Schnöll, Matthias Bittner, Maximilian Götzinger, Axel Jantsch. 53-60 [doi]
• A Method to Construct Efficient Carbon-Nanotube-Based Physical Unclonable Functions and True Random Number GeneratorsNikolaos Athanasios Anagnostopoulos, Nico Mexis, Simon Böttger, Martin Hartmann, Ali Mohamed, Sascha Hermann, Stefan Katzenbeisser 0001, Stavros G. Stavrinides, Tolga Arul. 61-69 [doi]
• Spatial Correlation in Weak Physical Unclonable Functions: A Comprehensive OverviewNico Mexis, Tolga Arul, Nikolaos Athanasios Anagnostopoulos, Florian Frank, Simon Böttger, Martin Hartmann, Sascha Hermann, Elif Bilge Kavun, Stefan Katzenbeisser 0001. 70-78 [doi]
• A Sketch-Based Algorithm for Network-Flow Entropy Estimation on Programmable Switches Using P4Javier E. Soto, Sofía Vera, Yaime Fernández, Daniel Yunge, Cecilia Hernández, Miguel E. Figueroa. 79-86 [doi]
• A Pre-Silicon Power Leakage Assessment Based on Generative Adversarial NetworksAbdullah Aljuffri, Mudit Saxena, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil. 87-94 [doi]
• Radar-Based Human Activity Acquisition, Classification and Recognition Towards Elderly Fall PredictionClaire Fenouillet-Béranger, Alexandre Bordat, Mohamed Amine Khelif, Petr Dobiás, Ngoc-Son Vu, Julien Le Kernec, David Guyard, Olivier Romain. 95-102 [doi]
• Novel Approach for AI-Based Risk Calculator Development Using Transfer Learning Suitable for Embedded SystemsAntonio J. Rodríguez-Almeida, Himar Fabelo, Cristina Soguero-Ruíz, Rosa María Sanchez-Hernandez, Ana M. Wägner, Gustavo Marrero Callicó. 103-110 [doi]
• An Attention-Based Parallel Algorithm for Hyperspectral Skin Cancer Classification on Low-Power GPUsEmanuele Torti, Marco Gazzoni, Elisa Marenzi, Raquel León, Gustavo Marrero Callicó, Giovanni Danese, Francesco Leporati. 111-116 [doi]
• GCells: A Graph-Search Approach to Design Custom Cells for Computational SubsystemsMayank Kabra, Shreyas V. S, Prashanth H. C., Kedar Deshpande, Madhav Rao. 117-123 [doi]
• Single-Trace Attack on NTRU Decryption with Machine Learning and Template ProfilingTomás Rabas, Jirí Bucek, Róbert Lórencz. 124-129 [doi]
• VADAR: A Vision-based Anomaly Detection Algorithm for RailroadsDavid Breuss, Maximilian Götzinger, Jenny Vuong, Clemens Reisner, Axel Jantsch. 130-137 [doi]
• On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN AcceleratorsYamilka Toca-Díaz, Nicolás Landeros Muñoz, Ruben Gran Tejero, Alejandro Valero. 138-145 [doi]
• Optimization of the Versatile Tensor Accelerator (VTA) Load Module in a Time-Triggered Memory AccessAniebiet Micheal Ezekiel, Daniel Onwuchekwa, Roman Obermaisser. 146-152 [doi]
• FPGA-tidbits: Rapid Prototyping of FPGA Accelerators in ChiselErling Rennemo Jellum, Yaman Umuruglu, Milica Orlandic, Martin Schoeberl. 153-160 [doi]
• Towards Deploying Highly Quantized Neural Networks on FPGA Using ChiselJure Vreca, Anton Biasizzo. 161-167 [doi]
• Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click ElementsKasper Hesse, Tjark Petersen, Jens Sparsø. 168-175 [doi]
• The IoTwins Methodology and Platform to Implement and Operate Digital Twins-based I4.0 Applications in the Cloud ContinuumPaolo Bellavista, Giuseppe Di Modica. 176-183 [doi]
• DevOps for Cyber-Physical Systems: Objectives, Results and Lessons Learned from the Adeptness H2020 ProjectAitor Arrieta, Goiuria Sagardui, Aitor Agirre, Wasif Afzal, Shaukat Ali 0001. 184-189 [doi]
• COMP4DRONES Contributions for Enabling Safe and Autonomous DronesRéda Nouacer, Guillaume Ollier, Mahmoud Hussein. 190-197 [doi]
• Deterministic Search Strategy of Compression CodesOndrej Novák. 198-205 [doi]
• Towards Resilient Quasi Delay Insensitive Conditional Control ElementsZaheer Tabassam, Andreas Steininger. 206-213 [doi]
• Targeting different defect-oriented fault models in IC testing: an experimental approachNunzio Mirabella, Andrea Floridia, Riccardo Cantoro, Michelangelo Grosso, Matteo Sonza Reorda. 214-219 [doi]
• Disparity Refinement Processor Architecture Utilizing Horizontal and Vertical Characteristics for Stereo Vision SystemsCheol Ho Choi, Hyun Woo Oh. 220-226 [doi]
• Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML ApplicationsMounika Vaddeboina, Endri Kaja, Alper Yilmayer, Sebastian Prebeck, Wolfgang Ecker. 227-234 [doi]
• Latency-Optimized Hardware Acceleration of Multilayer Perceptron InferenceAhmad Al-Zoubi, Benedikt Schaible, Gianluca Martino, Görschwin Fey. 235-241 [doi]
• On the Feasibility of using FPGA's for Efficient Topology OptimizationKasper Hesse, Martin Schoeberl, Niels Aage, Erik Träff. 242-250 [doi]
• A Modular Open-Source Cryptographic Co-Processor for Internet of ThingsDina Hesse, Maël Gay, Ilia Polian, Elif Bilge Kavun, Owen Millwood, Witali Bartsch. 251-259 [doi]
• Active learning for fast and slow modeling attacks on Arbiter PUFsVincent Dumoulin, Wenjing Rao, Natasha Devroye. 260-268 [doi]
• Software-Only Control-Flow Integrity Against Fault Injection AttacksFrançois Bonnal, Vincent Dupaquis, Olivier Potin, Jean-Max Dutertre. 269-277 [doi]
• Characterizing Intrusion Detection Systems On Heterogeneous Embedded PlatformsCamélia Slimani, Louis Morge-Rollet, Laurent Lemarchand, Frédéric Le Roy, David Espes, Jalil Boukhobza. 278-285 [doi]
• Towards a Smart Multi-Sensor Ionizing Radiation Monitoring SystemMarko S. Andjelkovic, Junchao Chen 0001, Rizwan Tariq Syed, Fabian Vargas 0001, Markus Ulbricht 0002, Milos Krstic, Stefan D. Ilic, Milos Marjanovic, Sandra Veljkovic, Nikola Mitrovic, Danijel Dankovic, Goran S. Ristic, Russell Duane, Nikola Vasovic, Aleksandar Jaksic, Alberto J. Palma, Antonio M. Lallena, Miguel A. Carvajal. 286-293 [doi]
• Acceleration of a CNN-based Heart Sound Segmenter: Implementation on Different Platforms Targeting a Wearable DeviceDomenico Ragusa, Antonio J. Rodríguez-Almeida, Stephan Nolting, Emanuele Torti, Himar Fabelo, Ingo Hoyer, Alexander Utz, Gustavo Marrero Callicó, Francesco Leporati. 294-301 [doi]
• VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud ServicesRamon Canal, Cristiano Pegoraro Chenet, Aggelos Arelakis, José María Arnau, Josep Lluís Berral, Aaron Call, Stefano Di Carlo, Juan José Costa, Dimitris Gizopoulos, Vasileios Karakostas, Francesco Lubrano, Konstantinos Nikas, Yiannis Nikolakopoulos, Beatriz Otero, George Papadimitriou 0001, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Daniel Raho, Alvise Rigo, Eva Rodríguez, Alessandro Savino, Alberto Scionti, Nikolaos Tampouratzis, Alex Torregrosa. 302-308 [doi]
• A Novel Real-Time Framework for Embedded Systems Health MonitoringJuliano Pimentel, Alistair A. McEwan, Hong Qing Yu. 309-316 [doi]
• Fault Injection on Embedded Neural Networks: Impact of a Single Instruction SkipClément Gaine, Pierre-Alain Moëllic, Olivier Potin, Jean-Max Dutertre. 317-324 [doi]
• Fault-Tolerant Lightweight High Level ArchitectureDaniel Onwuchekwa, Krishi Savla, Devika Joshi, Roman Obermaisser, Tobias Pieper. 325-334 [doi]
• Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine LearningLeandro Lanzieri, Peter Kietzmann, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt. 335-342 [doi]
• ComCoS: Enhanced Cache Partitioning Technique for Integrated Modular AvionicsYakup Hüner, Ramazan Yeniçeri. 343-350 [doi]
• The Last-Level-Cache Interference in Guest Performance: a Case-Study with Zephyr OSMarcelo Ruaro, Hadrien Barral, Matteo Bertolino, Rodrigo Cataldo, Roberto Medina 0001, Mohamed Karaoui, Etienne Borde. 351-358 [doi]
• Utilizing Prefetch Buffers for Iterative Graph ApplicationsBurak Ocalan, Ozcan Ozturk 0001. 359-365 [doi]
• Unraveling the Mystery of NVIDIA's Unified Memory for Safety-Critical GPU SystemsXabier Arauzo, Irune Yarza, Leonidas Kosmidis, Alejandro J. Calderón, Marcos Rodriguez. 366-372 [doi]
• Implementation of an Assignment Algorithm for Object Tracking on a FPGA MPSoCDenis Shemonaev, Bertrand Le Gal, Christophe Jégo, Anthony Besseau. 373-380 [doi]
• A Hybrid Delay Model for Interconnected Multi-Input GatesArman Ferdowsi, Matthias Függer, Josef Salzmann, Ulrich Schmid 0001. 381-390 [doi]
• Access Interval Prediction with Neural Networks for Tightly Coupled Memory SystemsSimon Friedrich, Chia-Ying Lin, Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis. 391-398 [doi]
• UP2DATE software updating framework compliance with safety and security regulations and standardsIrune Agirre, Alejandro J. Calderón, Irune Yarza, Imanol Mugarza, David García Villaescusa, Lucas Borracci, Patrick Uven, Alvaro Jover-Alvarez. 399-406 [doi]
• Demonstrator Development of a Next-Generation Video Instrument for Earth ObservationYubal Barrios, Francisco Sanjuan, Geoffroy Bordot, Helia Sharif, Jerome Bernier, Sebastián López. 407-414 [doi]
• OPTIMIST: Optimised Video Content Delivery Chains over Joint Multi-Access Edge Computing and 5G Radio Network InfrastructuresDionysis Xenakis, Carlo Centofanti, Claudia Rinaldi, Andrea Marotta, Christos V. Verikoukis, Nikos I. Passas, Stefano Tennina, Dajana Cassioli. 415-421 [doi]
• Zenoh: Unifying Communication, Storage and Computation from the Cloud to the MicrocontrollerAngelo Corsaro, Luca Cominardi, Olivier Hecart, Gabriele Baldoni, Julien Enoch Pierre Avital, Julien Loudet, Carlos Guimares, Michael Ilyin, Dmitrii Bannov. 422-428 [doi]
• Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPUGianmarco Ottavi, Florian Zaruba, Luca Benini, Davide Rossi. 429-435 [doi]
• Automatic Deployment of Embedded Real-Time Software Systems to Hypervisor-Managed PlatformsFlorian Schade, Tobias Dörr, Alexander Ahlbrecht, Vincent Janson, Umut Durak, Jürgen Becker 0001. 436-443 [doi]
• Container Scheduling Under ARINC 653 Scheduler ConstraintsMehmet Sirin Onen, Arda Yurdakul. 444-451 [doi]
• Change of Plans: Optimizing for Power, Reliability and Timeliness for Cost-Conscious Real-Time SystemsLukas Miedema, Clemens Grelck. 452-461 [doi]
• AnTiQ: A Hardware-Accelerated Priority Queue Design with Constant Time Arbitrary Element RemovalAntti Nurmi, Per Lindgren, Tom Szymkowiak, Timo D. Hämäläinen. 462-469 [doi]
• High Performance and Energy Efficient AMD and BWAD Pooling Schemes Characterised for CNN AcceleratorsVinay Rayapati, Mahati Basavaraju, Madhav Rao. 470-477 [doi]
• FPGA based 77GHz RADAR processing with novel linearisationPeter Hobden, Saket Srivastava, Edmond Nurellari. 478-484 [doi]
• Transmittance Hyperspectral Capture System and Methodology Assessment for Blood-Liquid Serum Samples AnalysisGonzalo Rosa, Cristina Sánchez Carabias, Victoria Cunha Alves, Manuel Villa, Alberto Martín-Pérez, Miguel Chavarrías, Alfonso Lagares, Eduardo Juárez 0001, César Sanz. 485-492 [doi]
• Evaluation of Hyperspectral Imaging Fusion for in-vivo Brain Tumor Identification and DelineationRaquel León, Himar Fabelo, Samuel Ortega, Juan F. Piñeiro, Adam Szolna, Jesús Morera, Bernardino Clavo, Gustavo Marrero Callicó. 493-499 [doi]
• Analysis of the Behavior of Ozone Therapy in Chemotherapy-Induced Neuropathy Using Hyperspectral Imaging TechnologyBeatriz Martínez-Vega, Raquel León, Himar Fabelo, Samuel Ortega, Eduardo Quevedo, Angeles Canovas-Molina, Francisco Rodriguez-Esparagon, Bernardino Clavo, Gustavo Marrero Callicó. 500-506 [doi]
• Real-Time Hyperspectral and Depth Fusion Calibration Method for Improved Reflectance Measures on Arbitrary Complex SurfacesAlejandro Martinez de Ternero, Jaime Sancho, Alberto Martín-Pérez, Manuel Villa, Guillermo Vázquez, Pedro L. Cebrián, Gonzalo Rosa, Pallab Sutradhar, Miguel Chavarrías, Eduardo Juárez 0001, César Sanz. 507-514 [doi]
• Real-Time Independent Components Analysis for Dimensional Reduction of Hyperspectral Images Using Reconfigurable HardwareDaniel Fernandez, Carlos González 0002, Daniel Mozos. 515-522 [doi]
• Polymorphic RTL Computational ElementsRichard Ruzicka, Václav Simek, Jan Nevoral. 523-530 [doi]
• Minimizing the Impact of Unbalanced Splitting Errors on DMFBs Without Any OverheadYuji Wada, Shigeru Yamashita. 531-538 [doi]
• Efficient Simulation of Droplet Merging in Channel-Based Microfluidic DevicesGerold Fink, Florina Costamoling, Philipp Ebner, Robert Wille. 539-544 [doi]
• A PQC and QKD Hybridization for Quantum-Secure CommunicationsDominik Marchsreiter, Johanna Sepúlveda. 545-552 [doi]
• Secure Data Acquisition for Battery Management SystemsFikret Basic, Christian Seifert, Christian Steger, Robert Kofler. 553-560 [doi]
• Mitigating Masking in Automotive Communication Systems: Modeling and Hardware GenerationMatthias Stammler, Matthias Hamann, Tanja Harbaum, Jürgen Becker 0001. 561-568 [doi]
• ATLAS: An Approximate Time-Series LSTM Accelerator for Low-Power IoT ApplicationsFabian Kreß, Alexey Serdyuk, Micha Hiegle, Disnebio Waldmann, Tim Hotfilter, Julian Höfer, Tim Hamann, Jens Barth, Peter Kämpf, Tanja Harbaum, Jürgen Becker 0001. 569-576 [doi]
• Auto-DOK: Compiler-Assisted Automatic Detection of Offload Kernels for FPGA-HBM ArchitecturesVeronia Iskandar, Mohamed A. Abd El ghany, Diana Goehringer. 577-584 [doi]
• RTASS: a RunTime Adaptable and Scalable System for Network-on-Chip-Based ArchitecturesNajdet Charaf, Julian Haase, Adrian Kulisch, Christian von Elm, Diana Göhringer. 585-592 [doi]
• An Ontological Approach for the Dependability Analysis of Automated SystemsGuillaume Ollier, Morayo Adedjouma, Simos Gerasimou, Chokri Mraidha. 593-601 [doi]
• Enhancing the Availability of Web Services in the IoT-to-Edge-to-Cloud Compute Continuum: A WordPress Case StudyGabriele Serra, Pietro Fara, Daniel Casini. 602-609 [doi]
• SimIoT: A Simulator for Verification and Profiling of Complex IoT DeploymentsJosé Antonio de la Torre, Fernando Rincón, Marco Zennaro, Julián Caba, Jesús Barba, Juan Carlos López 0001. 610-617 [doi]
• Bounded transmission latency in real-time edge computing: a scheduling analysisPietro Fara, Gabriele Serra, Federico Aromolo. 618-625 [doi]
• A Novel Memristive-Based Data Reordering SchemeMojtaba Mahdavi. 626-633 [doi]
• Memristor-Based Lightweight EncryptionMuhammad Ali Siddiqi, Jan Andrés Galvan Hernández, Anteneh Gebreziorgis, Rajendra Bishnoi, Christos Strydis, Said Hamdioui, Mottaqiallah Taouil. 634-641 [doi]
• Exact Dot Product Accumulate Operators for 8-bit Floating-Point Deep LearningOrégane Desrentes, Benoît Dupont de Dinechin, Julien Le Maire. 642-649 [doi]
• A RISC-V based platform supporting mixed timing-critical and high performance workloadsMehrdad Poorhosseini, Kim Grüttner. 650-659 [doi]
• An SoC FPGA-based Integrated Real-time Image Processor for Uncooled Infrared Focal Plane ArrayHyun Woo Oh, Cheol Ho Choi, Jeong Woo Cha, HyunMin Choi, Joonhwan Han, Jungho Shin. 660-668 [doi]
• Seto: A Framework for the Decomposition of Petri Nets and Transition SystemsViktor Teren, Jordi Cortadella, Tiziano Villa. 669-677 [doi]
• Integration of the TPM in the AACKA ProtocolRaphael Schermann, Rainer Urian, Christian Steger. 678-685 [doi]
• DSLOT-NN: Digit-Serial Left-to-Right Neural Network AcceleratorMuhammad Sohail Ibrahim, Muhammad Usman, Malik Zohaib Nisar, Jeong-A Lee. 686-692 [doi]
• Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V ProcessorsWeiyan Zhang, Mehran Goli, Muhammad Hassan 0002, Rolf Drechsler. 693-699 [doi]
• Fast, Quantization Aware DNN Training for Efficient HW ImplementationDaniel Schnöll, Matthias Wess, Matthias Bittner, Maximilian Götzinger, Axel Jantsch. 700-707 [doi]
• Non-Profiled Semi-Supervised Horizontal Attack Against Elliptic Curve Scalar Multiplication Using Support Vector MachinesMarcin Aftowicz, Ievgen Kabin, Zoya Dyka, Peter Langendörfer. 708-713 [doi]
• FPGA-Based Encryption System for Cloud SecurityMarios Papadopoulos, Paris Kitsos. 714-717 [doi]
• A Non Profiled and Profiled Side Channel Attack Countermeasure through Computation InterleavingIsabella Piacentini, Alessandro Barenghi, Gerardo Pelosi. 718-725 [doi]
• Virtualization of Hardware Accelerators in a Network-on-ChipCornelia Wulf, Julian Haase, Matthias Nickel, Diana Göhringer. 726-733 [doi]
• Formal Property Verification for Early Discovery of Functional Flaws in Digital Designs: A Designer's GuideMeinhard Kissich, Marcel Baunach. 734-741 [doi]
• Vision-Based Multi-Size Object PositioningVibhor Jain, Sajid Mohamed, Dip Goswami, Sander Stuijk. 742-747 [doi]
• Investigating the Impact of Non-Volatile Memories on Energy-Efficiency of Coarse-Grained Reconfigurable ArchitecturesEnsieh Aliagha, Veronia Iskandar, Stephan Enseleit, Diana Göhringer. 748-755 [doi]
• A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core ProcessorsLilia Zaourar, Alice Chillet, Jean-Marc Philippe. 756-763 [doi]
• MPSoC FPGA Implementation of Algorithms of Machine Learning for Clinical Applications Using High-Level Design MethodologyMario Guanche-Hernández, Raquel León, Pedro P. Carballo. 764-769 [doi]
• CFD for Microfluidics: A Workflow for Setting Up the Simulation of Microfluidic DevicesPhilipp Ebner, Robert Wille. 770-775 [doi]
• Compact Quantum Circuits for Dimension Reducible FunctionsAnna Bernasconi 0001, Valentina Ciriani, Asma Taheri Monfared, Stefano Zanoni. 776-781 [doi]
• Implementation and Verification of the Argo Network-on-Chip in ChiselKasper Hesse. 782-787 [doi]