Table of Contents

• A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable SupercomputerGerald R. Morris, Viktor K. Prasanna, Richard D. Anderson. 3-12 [doi]
• A case study in porting a production scientific supercomputing application to a reconfigurable computerVolodymyr V. Kindratenko, David Pointer. 13-22 [doi]
• Hardware/Software Approach to Molecular Dynamics on Reconfigurable ComputersRonald Scrofano, Maya Gokhale, Frans Trouw, Viktor K. Prasanna. 23-34 [doi]
• Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAsChun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo. 35-44 [doi]
• Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C FunctionsDavid J. Lau, Orion Pritchard, Philippe Molson. 45-56 [doi]
• Efficient Hardware Generation of Random Variates with Arbitrary DistributionsDavid B. Thomas, Wayne Luk. 57-66 [doi]
• An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing SystemsZachary K. Baker, Viktor K. Prasanna. 67-75 [doi]
• Automatic Sliding Window Operation Optimization for FPGA-BasedHaiqian Yu, Miriam Leeser. 76-88 [doi]
• Enabling a Uniform Programming Model Across the Software/Hardware BoundaryErik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David L. Andrews. 89-98 [doi]
• A Type Architecture for Hybrid Micro-Parallel ComputersBenjamin Ylvisaker, Brian Van Essen, Carl Ebeling. 99-110 [doi]
• A Scalable FPGA-based MultiprocessorArun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Regis Pomes, Paul Chow. 111-120 [doi]
• A Reconfigurable Distributed Computing Fabric Exploiting Multilevel ParallelismCharles L. Cathey, Jason D. Bakos, Duncan A. Buell. 121-130 [doi]
• A Multithreaded Soft Processor for SoPC Area ReductionBlair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown. 131-142 [doi]
• GraphStep: A System Architecture for Sparse-Graph AlgorithmsMichael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas E. Uribe, Thomas F. Knight Jr., André DeHon. 143-151 [doi]
• Hardware/Software Integration for FPGA-based All-Pairs Shortest-PathsUday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan. 152-164 [doi]
• A Field Programmable RFID Tag and Associated Design FlowAlex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle. 165-174 [doi]
• Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGARobert G. Dimond, Oskar Mencer, Wayne Luk. 175-184 [doi]
• Power Visualization, Analysis, and Optimization Tools for FPGAsMatthew French, Li Wang, Michael J. Wirthlin. 185-194 [doi]
• Systematic Characterization of Programmable Packet Processing PipelinesMichael Attig, Gordon J. Brebner. 195-204 [doi]
• Packet Switched vs. Time Multiplexed FPGA Overlay NetworksNachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon. 205-216 [doi]
• Single Pass, BLAST-Like, Approximate String Matching on FPGAsMartin C. Herbordt, Josh Model, Yongfeng Gu, Bharat Sukhwani, Tom Van Court. 217-226 [doi]
• An FPGA Solution for Radiation Dose CalculationKevin Whitton, Xiaobo Sharon Hu, Cedric X. Yu, Danny Z. Chen. 227-236 [doi]
• A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)Andrey Bogdanov, M. C. Mertens. 237-248 [doi]
• Advanced Components in the Variable Precision Floating-Point LibraryXiaojun Wang, Sherman Braganza, Miriam Leeser. 249-258 [doi]
• Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision ComponentsRobert Strzodka, Dominik Göddeke. 259-270 [doi]
• ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only SkillsEvgeny Fiksman, Yitzhak Birk, Oskar Mencer. 271-272 [doi]
• COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAsShannon Koh, Oliver Diessel. 273-274 [doi]
• A Novel Hueristic and Provable Bounds for Reconfigurable Architecture DesignAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. 275-276 [doi]
• Defect-Tolerant Nanocomputing Using Bloom FiltersGang Wang, Wenrui Gong, Ryan Kastner. 277-278 [doi]
• A Programmable, Maximal Throughput Architecture for Neighborhood Image ProcessingReid B. Porter, Jan R. Frigo, Maya Gokhale, Christophe Wolinski, François Charot, Charles Wagner. 279-280 [doi]
• VPN Acceleration Using Reconfigurable System-On-Chip TechnologyChin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams. 281-282 [doi]
• An Optimized Finite Difference Computing Engine on FPGAsChuan He, Guan Qin, Mi Lu, Wei Zhao. 283-284 [doi]
• Highly Efficient String Matching Circuit for IDS with FPGAToshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi. 285-286 [doi]
• Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA ArchitecturesRafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez. 287-288 [doi]
• Scheduling divisible loads on partially reconfigurable hardwareK. N. Vikram, V. Vasudevan. 289-290 [doi]
• General Architecture for Hardware Implementation of Genetic AlgorithmTatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito. 291-292 [doi]
• Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAsYousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos. 293-294 [doi]
• Scalable Softcore Vector Processor for Biosequence ApplicationsArpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho. 295-296 [doi]
• Generating Parametrised Hardware Libraries from Higher-Order DescriptionsOliver Pell, Wayne Luk. 297-298 [doi]
• Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones. 299-300 [doi]
• Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid DynamicsGerhard Lienhart, Guillermo Marcus Martinez, Andreas Kugel, Reinhard Männer. 301-302 [doi]
• Floating-Point Accumulation Circuit for Matrix ApplicationsMichael R. Bodnar, John R. Humphrey, Petersen F. Curt, James P. Durbano, Dennis W. Prather. 303-304 [doi]
• Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid ComputationsTom Van Court, Martin C. Herbordt. 305-306 [doi]
• A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable SystemsKyprianos Papademetriou, Apostolos Dollas. 307-308 [doi]
• A Low-Energy Reconfigurable Fabric for the SuperCISC ArchitectureGayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones. 309-310 [doi]
• COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-BreakingSandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler. 311-312 [doi]
• FPGAs, GPUs and the PS2 - A Single Programming MethodologyLee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann. 313-314 [doi]
• Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary ReportYongfeng Gu, Tom Van Court, Martin C. Herbordt. 315-316 [doi]
• A Co-Verification Tool for a High Level Language Compiler for FPGAsCharlie Ross, A. P. Wim Böhm. 317-318 [doi]
• Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime ReconfigurationDionissios Efstathiou, Konstantinos Kazakos, Apostolos Dollas. 319-320 [doi]
• Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital DevicesJohn Maher, Brian McGinley, Patrick Rocke, Fearghal Morgan. 321-322 [doi]
• The STAR-C Truth: Analyzing Reconfigurable Supercomputing ReliabilityHeather Quinn, Debayan Bhaduri, Christof Teuscher, Paul Graham, Maya Gokhale. 323-324 [doi]
• Pre-synthesis Queue Size Estimation of Streaming Data Flow GraphsSomsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas. 325-326 [doi]
• Hierarchical Clustering using Reconfigurable DevicesShobana Padmanabhan, Moshe Looks, Dan Legorreta, Young H. Cho, John W. Lockwood. 327-328 [doi]
• CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future ArchitecturesS. Dai, Elaheh Bozorgzadeh. 329-330 [doi]
• A Scalable Architecture for RSA Cryptography on Large FPGAsAllen Michalski, Duncan A. Buell. 331-332 [doi]
• Design of a Reconfigurable Processor for NIST Prime Field ECCKendall Ananyi, Daler N. Rakhmatov. 333-334 [doi]
• Switch Box Architectures for Three-Dimensional FPGAsAman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman. 335-336 [doi]
• A Scalable Hybrid Regular Expression Pattern MatcherJames Moscola, Young H. Cho, John W. Lockwood. 337-338 [doi]
• Hardware/Software Co-Design Architecture for Lattice Decoding AlgorithmsCao Liang, Jing Ma, Xin-Ming Huang. 339-340 [doi]
• High Performance Feature Detection on a Reconfigurable Co-ProcessorJia Ming Mar, Alessandro Bissacco, Stefano Soatto, Soheil Ghiasi. 341-342 [doi]
• DSynth: A Pipeline Synthesis Environment for FPGAsMichael J. Wirthlin, Welson Sun. 343-344 [doi]
• Template-Based Generation of Streaming Accelators from a High Level PresentationNikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier. 345-346 [doi]
• Scalable Hardware Architecture for Real-Time Dynamic Programming ApplicationsBrad Matthews, Itamar Elhanany. 347-348 [doi]
• Open Source High Performance Floating-Point ModulesK. Scott Hemmert, Keith D. Underwood. 349-350 [doi]
• A Reconfigurable Cluster-on-Chip Architecture with MPI Communication LayerJohn A. Williams, Irfan Syed, J. Wu, Neil W. Bergmann. 351-352 [doi]