Abstract is missing.
- On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat)Michael Caffrey, Keith Morgan, Diane Roussel-Dupre, Scott Robinson, Anthony Nelson, Anthony Salazar, Michael J. Wirthlin, William Howes, Daniel Richins. 3-10 [doi]
- Accelerating Cosmological Data Analysis with FPGAsVolodymyr V. Kindratenko, Robert J. Brunner. 11-18 [doi]
- FPGA Design Analysis of the Clustering Algorithm for the CERN Large Hadron ColliderAnthony E. Gregerson, Amin Farmahini Farahani, Ben Buchli, Steve Naumov, Michail Bachtis, Katherine Compton, Michael J. Schulte, Wesley H. Smith, Sridhara Dasu. 19-26 [doi]
- Accelerating Quadrature Methods for Option ValuationAnson H. T. Tse, David B. Thomas, Wayne Luk. 29-36 [doi]
- Accelerating SPICE Model-Evaluation using FPGAsNachiket Kapre, André DeHon. 37-44 [doi]
- FPGA Accelerated Simulation of Biologically Plausible Spiking Neural NetworksDavid Thomas, Wayne Luk. 45-52 [doi]
- Generic Software Framework for Adaptive Applications on FPGAsSuhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda Doyle, Robert Esser. 55-62 [doi]
- Block, Drop or Roll(back): Alternative Preemption Methods for RH Multi-TaskingKyle Rupnow, Wenyin Fu, Katherine Compton. 63-70 [doi]
- Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication SystemsAmir Hossein Gholamipour, Hamid Eslami, Ahmed M. Eltawil, Fadi J. Kurdahi. 71-78 [doi]
- CAAD BLASTP: NCBI BLASTP Accelerated with FPGA-Based Accelerated Pre-FilteringJin H. Park, Yunfei Qiu, Martin C. Herbordt. 81-87 [doi]
- RC-BLASTn: Implementation and Evaluation of the BLASTn Scan FunctionSiddhartha Datta, Parag Beeraka, Ron Sass. 88-95 [doi]
- Multi-Core Architecture on FPGA for Large Dictionary String MatchingQingbo Wang, Viktor K. Prasanna. 96-103 [doi]
- Memory-Efficient Pipelined Architecture for Large-Scale String MatchingYi-Hua Edward Yang, Viktor K. Prasanna. 104-111 [doi]
- A Massively Parallel FPGA-Based Coprocessor for Support Vector MachinesSrihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar, Hans Peter Graf. 115-122 [doi]
- Application Specific Customization and Scalability of Soft MultiprocessorsDeepak Unnikrishnan, Jia Zhao, Russell Tessier. 123-130 [doi]
- Benchmarking Reconfigurable Architectures in the Mobile DomainPeter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen. 131-138 [doi]
- Optical Flow on the Ambric Massively Parallel Processor Array (MPPA)Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis. 141-148 [doi]
- Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming AcceleratorsNikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier. 149-156 [doi]
- FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer TherapyJason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose. 157-164 [doi]
- Scalable High Throughput and Power Efficient IP-Lookup on FPGAHoang Le, Viktor K. Prasanna. 167-174 [doi]
- Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing SystemsPaul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede. 175-182 [doi]
- A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAsGuiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang. 183-190 [doi]
- Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable DevicesSamuel Antao, Ricardo Chaves, Leonel Sousa. 193-200 [doi]
- Non-Preconditioned Conjugate Gradient on Cell and FPGA Based Hybrid Supercomputer NodesDavid DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor Davenport. 201-208 [doi]
- More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive ControlAntonio Roldao Lopes, Amir Shahzad, George A. Constantinides, Eric C. Kerrigan. 209-216 [doi]
- In-situ FPGA Debug Driven by On-Board MicrocontrollerZachary K. Baker, Joshua S. Monson. 219-222 [doi]
- Exploiting Matrix Symmetry to Improve FPGA-Accelerated Conjugate GradientJason D. Bakos, Krishna K. Nagar. 223-226 [doi]
- Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable ComputerJong-Ho Byun, Arun Ravindran, Arindam Mukherjee, Bharat Joshi, David Chassin. 227-230 [doi]
- Evaluation of Static Analysis Techniques for Fixed-Point Precision OptimizationJason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou. 231-234 [doi]
- A Packet Generator on the NetFPGA PlatformG. Adam Covington, Glen Gibb, John W. Lockwood, Nick McKeown. 235-238 [doi]
- Shared Memory Cache Organizations for Reconfigurable Computing SystemsPhilip Garcia, Katherine Compton. 239-242 [doi]
- Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor NetworksRafael Garcia, Ann Gordon-Ross, Alan D. George. 243-246 [doi]
- Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture VariantsMiaoqing Huang, Vikram K. Narayana, Tarek A. El-Ghazawi. 247-250 [doi]
- Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble SystemsDirk Koch, Christian Beckhoff, Jürgen Teich. 251-254 [doi]
- Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUsHolger Lange, Florian Stock, Andreas Koch, Dietmar Hildenbrand. 255-258 [doi]
- FPGA Floating Point Datapath CompilerMartin Langhammer, Tom VanCourt. 259-262 [doi]
- A Parameterized Stereo Vision Core for FPGAsStephen Longfield Jr., Mark L. Chang. 263-266 [doi]
- FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle AccumulationArun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne. 267-270 [doi]
- AIREN: A Novel Integration of On-Chip and Off-Chip FPGA NetworksAndrew G. Schmidt, William V. Kritikos, Rahul R. Sharma, Ron Sass. 271-274 [doi]
- IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable ComputingTobias Schumacher, Christian Plessl, Marco Platzner. 275-278 [doi]
- Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA AcceleratorsJoon Edward Sim, Weng-Fai Wong, Jürgen Teich. 279-282 [doi]
- Employment of Reduced Precision Redundancy for Fault Tolerant FPGA ApplicationsMargaret A. Sullivan, Herschel H. Loomis Jr., Alan A. Ross. 283-286 [doi]
- HighKostas Theoharoulis, Charalampos Manifavas, Ioannis Papaefstathiou. 287-290 [doi]
- Application Experiments: MPPA and FPGAPhilip Top, Maya Gokhale. 291-294 [doi]
- FPGA Implementation of the Interior-Point Algorithm with Applications to Collision DetectionChih-Hung Wu, Seda Ogrenci Memik, Sanjay Mehrotra. 295-298 [doi]
- Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case StudyJason Wu, John W. Williams, Neil W. Bergmann, Peter Sutton. 299-302 [doi]
- An FPGA Implementation for Solving Least Square ProblemDepeng Yang, Gregory D. Peterson, Husheng Li, Junqing Sun. 303-306 [doi]