Table of Contents

• On the Malicious Potential of Xilinx' Internal Configuration Access Port (ICAP)Nils Albartus, Maik Ender, Jan-Niklas Möller, Marc Fyrbiak, Christof Paar, Russell Tessier. 1 [doi]
• Covert-channels in FPGA-enabled SmartSSDsTheodoros Trochatos, Anthony Etim, Jakub Szefer. 2 [doi]
• Journal Track Paper ICFPT 2023 : HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural NetworksGeng Yang, Jie Lei 0001, Zhenman Fang, Yunsong Li, Jiaqing Zhang, Weiying Xie. 3-4 [doi]
• Journal Track Paper ICFPT 2023 : Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAsEmanuele Del Sozzo, Davide Conficconi, Kentaro Sano. 5 [doi]
• AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQCTianyou Bao, Pengzhou He, Jiafeng Xie, H. S. Jacinto. 6 [doi]
• A Deep-Learning Data-Driven Approach for Reducing FPGA Routing RuntimesTimothy Martin, Q. Li, Charlotte Barnes, Gary Gréwal, Shawki Areibi. 7-15 [doi]
• A Tenant Side Compilation Solution for Cloud FPGA DeploymentMaximillian Panoff, Muhammed Kawser Ahmed, Hanqiu Wang, Shuo Wang 0003, Christophe Bobda. 16-25 [doi]
• GRAFT: GNN-based Adaptive Framework for Efficient CGRA MappingJiangnan Li, Chang Cai, Yaya Zhao, Yazhou Yan, Wenbo Yin, Lingli Wang. 26-34 [doi]
• BSTMSM: A High-Performance FPGA-based Multi-Scalar Multiplication Hardware AcceleratorBaoze Zhao, Wenjin Huang, Tianrui Li, Yihua Huang 0005. 35-43 [doi]
• FPGA-accelerated Quantum Transport MeasurementsTimo Haarman, Antonio Sousa de Almeida, Amber Heskes, Floris Zwanenburg, Nikolaos Alachiotis 0001. 44-52 [doi]
• An Efficient Dataflow for Convolutional Generative ModelsZhengzheng Ma, Guojie Luo. 53-59 [doi]
• PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based InferenceMarta Andronic, George A. Constantinides. 60-68 [doi]
• M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMsYuzong Chen, Jordan Dotzel, Mohamed S. Abdelfattah. 69-78 [doi]
• VIB: A Versatile Interconnection Block for FPGA Routing ArchitectureKaichuang Shi, Hao Zhou, Lingli Wang. 79-87 [doi]
• AUGER: A Multi-Objective Design Space Exploration Framework for CGRAsJingyuan Li, Yihan Hu, Yuan Dai, Huizhen Kuang, Lingli Wang. 88-95 [doi]
• MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI EngineEndri Taka, Aman Arora, Kai-Chiang Wu, Diana Marculescu. 96-105 [doi]
• HGBO-DSE: Hierarchical GNN and Bayesian Optimization based HLS Design Space ExplorationHuizhen Kuang, Xianfeng Cao, Jingyuan Li, Lingli Wang. 106-114 [doi]
• A High-Frequency Load-Store Queue with Speculative Allocations for High-Level SynthesisRobert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede. 115-124 [doi]
• Efficient FPGA-based Accelerator for Post-Processing in Object DetectionZibo Guo, Kai Liu, Wei Liu, Shangrong Li. 125-131 [doi]
• Extending Data Flow Architectures for Convolutional Neural Networks to Multiple FPGAsMohamed Ibrahim, Zhipeng Zhao, Mathew Hall, Vaughn Betz. 132-141 [doi]
• Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural ComparisonReilly McKendrick, Keenan Faulkner, Jeffrey Goeders. 142-151 [doi]
• Respect the Difference: Reinforcement Learning for Heterogeneous FPGA PlacementFatemehsadat Mahmoudi, Mohamed A. Elgammal, Soheil Gholami Shahrouz, Kevin E. Murray, Vaughn Betz. 152-160 [doi]
• SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAsQi Liu, Mo Sun, Jie Sun, Liqiang Lu, Jieru Zhao, Zeke Wang. 161-169 [doi]
• LUTNet-RC: Look-Up Tables Networks for Reservoir Computing on an FPGAKanta Yoshioka, Yuichiro Tanaka, Hakaru Tamukoh. 170-178 [doi]
• SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA DevicesAlexander Montgomerie-Corcoran, Petros Toupas, Zhewen Yu, Christos-Savvas Bouganis. 179-187 [doi]
• MERCURY: An Automated Remote Side-channel Attack to Nvidia Deep Learning AcceleratorXiaobei Yan, Xiaoxuan Lou, Guowen Xu, Han Qiu 0001, Shangwei Guo, Chip-Hong Chang, Tianwei Zhang 0004. 188-197 [doi]
• Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration DevicesAndrew Boutros, Fatemehsadat Mahmoudi, Amin Mohaghegh, Stephen More, Vaughn Betz. 198-208 [doi]
• Integrated Multi-Ported Memory Distribution for Temporal-Multiplexing Workloads on FPGAsChia-Chen Yen, Mi-Yen Yeh, Ming-Syan Chen. 209-216 [doi]
• OD-REM: On-Demand Regular Expression Matching on FPGAs for Efficient Deep Packet InspectionWeihai Xu, Zheng Zhou, Jin Zhang, Yiming Jiang, Peng Yi. 217-226 [doi]
• Asymmetry in Butterfly Fat Tree FPGA NoCDongjoon Park, Zhijing Yao, Yuanlong Xiao, André DeHon. 227-231 [doi]
• Accelerated Real-Time Classification of Evolving Data Streams using Adaptive Random ForestsFrank Ridder, Kuan-Hsun Chen, Nikolaos Alachiotis 0001. 232-237 [doi]
• SqueezeBlock: A Transparent Weight Compression Scheme for Deep Neural NetworksMo Song, Jiajun Wu 0007, Yuhao Ding, Hayden Kwok-Hay So. 238-243 [doi]
• Efficiently Removing Sparsity for High-Throughput Stream ProcessingPhilippos Papaphilippou, Zhiqiang Que, Wayne Luk. 244-249 [doi]
• Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAsKaichuang Shi, Hao Zhou, Lingli Wang. 250-253 [doi]
• An FPGA-GPU Heterogeneous System and Implementation for On-Board Remote Sensing Data ProcessingTingting Qiao, Yu Xie, He Chen, Yizhuang Xie. 254-257 [doi]
• An Extremely Pipelined FPGA-based accelerator of All Adder Neural Networks for On-board Remote Sensing Scene ClassificationNing Zhang, Shuo Ni, Tingting Qiao, Wenchao Liu, He Chen. 258-261 [doi]
• Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA ClustersRyota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase. 262-265 [doi]
• Traffic Flow Optimization using a Chaotic Boltzmann Machine Annealer on an FPGAKanta Yoshioka, Yuichiro Tanaka, Hakaru Tamukoh. 266-267 [doi]
• Kyokko: a Virtual channel capable Aurora 64B/66B compatible Serial Communication ControllerAkinobu Tomori, Yasunori Osana. 268-269 [doi]
• Offloading Image Recognition Processing for Care Robots to FPGA on Multi-access Edge ComputingHayato Mori, Eisuke Okazaki, Gai Nagahashi, Mikiko Sato, Takeshi Ohkawa, Midori Sugaya. 270-271 [doi]
• A state vector quantum simulator working on FPGAs with extensible SATA storageKaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi. 272-273 [doi]
• Stochastic Implementation of Simulated Quantum Annealing on PYNQTaiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu. 274-275 [doi]
• An FPGA-based Mix-grained Sparse Training AcceleratorYingchang Mao, Qiang Liu. 276-277 [doi]
• DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical FunctionsMoucheng Yang, Kaixiang Zhu, Lingli Wang, Xuegong Zhou. 278-279 [doi]
• F-TFM: Accelerating Total Focusing Method for Ultrasonic Array Imaging on FPGABizhao Shi, Jieran Zhang, Guojie Luo. 280-281 [doi]
• FPGA Resource-aware Structured Pruning for Real-Time Neural NetworksBenjamin Ramhorst, Vladimir Loncar, George A. Constantinides. 282-283 [doi]
• UAV Swarm Planning accelerator on FPGA with low latency and fixed-point L-BFGS Quasi-Newton solverSuquan Zhang, Jincheng Yu, Yuanfan Xu, Yu Wang 0002. 284-285 [doi]
• FPGA Framework Improvements for HPC ApplicationsAntonio Filgueras, Miquel Vidal, Daniel Jiménez-González, Carlos Álvarez 0001, Xavier Martorell. 286-287 [doi]
• Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storagesRyohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi. 288-289 [doi]
• Introducing the NAIL Accelerator Interface Layer for Low Latency FPGA OffloadEdward Grindley, Thurstan Gray, James Wilkinson, Chris Vaux, Adam Ardron, Jack Deeley, Alexander Elliott, Nidhin Thandassery Sumithran, Suhaib A. Fahmy. 290-291 [doi]
• Towards Asynchronously Triggered Spiking Neural Network on FPGA for Event-based VisionZhenyu Wu, Mo Song, Hayden Kwok-Hay So. 292-293 [doi]
• AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian OptimizationZhen Li, Hao Zhou, Lingli Wang, Xuegong Zhou. 294-295 [doi]
• 2-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End ToolchainYuhang Cao, Yunhui Qiu, Xuchen Gao, Qilong Zhu, Wenbo Yin, Lingli Wang. 296-297 [doi]
• A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel ApplicationsQilong Zhu, Yuhang Cao, Yunhui Qiu, Xuchen Gao, Wenbo Yin, Lingli Wang. 298-299 [doi]
• DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level SynthesisLiangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha. 300-301 [doi]
• OpenTitan based Multi-Level Security in FPGA System-on-ChipsSujan Kumar Saha, Abigail N. Butka, Muhammed Kawser Ahmed, Christophe Bobda. 302-303 [doi]