Table of Contents

• The path to embedded vision & AI using a low power vision DSPYair Siegel. 1-28 [doi]
• The era of high bandwidth memoryKevin Tran. 1-22 [doi]
• Deep compression and EIE: Efficient inference engine on compressed deep neural networkSong Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, Bill Dally. 1-6 [doi]
• Inuitive breakthrough solution for AR and VR worldsDor Zepeniuk. 1-14 [doi]
• Reconfigure your RTL with EFLX join the SoC revolutionCheng C. Wang, Dejan Markovic. 1-5 [doi]
• AnyCore-1: A comprehensively adaptive 4-way superscalar processorRangeen Basu Roy Chowdhury, Anil K. Kannepalli, Eric Rotenberg. 1 [doi]
• KiloCore: A 32 nm 1000-processor arrayBrent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas. 1-23 [doi]
• MvEcho - acoustic response modelling for auralisationLeonie Buckley, Sam Caulfield, David Moloney. 1 [doi]
• NOSQL hardware appliance with multiple data structureYuta Tokusashi, Hiroki Matsutani. 1 [doi]
• From model to FPGA: Software-hardware co-design for efficient neural network accelerationKaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han, Yu Wang, Huazhong Yang. 1-27 [doi]
• Design and development of a an ultra-low power Intel architecture MCU class SoCsPeter Barry. 1-29 [doi]
• Memory technology and applicationsAllen Rush. 1-14 [doi]
• Quantum dot based imagers for multispectral cameras and sensorsEmanuele Mandelli. 1-30 [doi]
• The future of graphic and mobile memory for new applicationsJin Kim. 1-25 [doi]
• A dynamically scheduled architecture for the synthesis of graph methodsMarco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi. 1-7 [doi]
• Experiences using a novel Python-based hardware modeling framework for computer architecture test chipsChristopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten. 1 [doi]
• Samsung exynos M1 processorBrad Burgess. 1-18 [doi]
• 3D reconstruction with tangoIvan Dryanovski. 1-24 [doi]
• Encoder logic for reducing serial I/O power in sensors and sensor hubsPhillip Stanley-Marbell, Pier Andrea Francese, Martin Rinard. 1-2 [doi]
• Helio X20: The first tri-gear mobile SoC with CorePilot™ 3.0 technologyTsung-Yao Lin, Ming-Hsien Lee, Loda Chou, Clavin Peng, Jih-Ming Hsu, Jia-Ming Chen, John-CC Chen, Alex Chiou, Artis Chiu, David Lee, Carrie Huang, Kenny Lee, TzuHeng Wang, Wei-Ting Wang, Yenchi Lee, Chi-Hui Wang, Pao-Ching Tseng, Ryan Chen, Kevin Jou. 1-24 [doi]
• Pascal GPU with NVLinkJohn Danskin, Denis Foley. 1-24 [doi]
• Modularizing the microprocessor core to outperform traditional out-of-orderTony Nowatzki, Karthikeyan Sankaralingam. 1-4 [doi]
• Embedded deep neural networks: "The cost of everything and the value of nothing"David Moloney. 1-20 [doi]
• A new ×86 core architecture for the next generation of computingMike Clark. 1-19 [doi]
• Passive dense stereo vision on the Myriad2 VPULuca Puglia, Mircea Ionica, Giancarlo Raiconi, David Moloney. 1-5 [doi]
• 3D sensors for the rest of usLarry Yang. 1-14 [doi]
• High performance DSP for vision, imaging and neural networksGreg Efland, Sandip Parikh, Himanshu Sanghavi, Aamir Farooqui. 1-30 [doi]
• A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO packageMu-Shan Lin, Chien-Chun Tsai, Cheng-Hsiang Hsieh, Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, Chin-Ming Fu, Hao-Jie Zhan, Jinn-Yeh Chien, Shao-Yu Li, Y. H. Chen, C.-C. Kuo, Shih-Peng Tai, Kazuyoshi Yamada. 1-32 [doi]
• Introducing "parker": Next-generation tegra system-on-chipAndi Skende. 1-17 [doi]
• VR and AR anytime and everywhere: Contributions of PMD depth sensing to an evolving ecosystemBernd Buxbaum. 1-19 [doi]
• ® LS1012A: Big things in small packages: 64-bit core in a sub-10mm packageBen Eckermann. 1-9 [doi]
• Memory as we approach a new horizonJ. Thomas Pawlowski. 1-23 [doi]
• Mobile 3D capture for professional applicationsRafael Spring. 1-38 [doi]
• The bifrost GPU architecture and the ARM Mali-G71 GPUJem Davies. 1-31 [doi]
• Piton: A 25-core academic manycore research processorMichael McKeown, Yaosheng Fu, Tri M. Nguyen, Yanqi Zhou, Jonathan Balkind, Alexey Lavrov, Mohammad Shahrad, Samuel Payne, David Wentzlaff. 1-38 [doi]
• SDA: Software-Defined Accelerator for general-purpose big data analysis systemJian Ouyang, Wei Qi, Yong Wang, YichenTu, Jing Wang, Bowen Jia. 1-23 [doi]
• An intelligent ADAS processor with real-time semi-global matching and intention prediction for 720p stereo visionKyuho Jason Lee, Kyeongryeol Bong, Changhyeon Kim, Hoi-Jun Yoo. 1 [doi]
• MvEchoLeonie Buckley, Sam Caulfield, David Moloney. 1-6 [doi]
• Task parallel programming model + hardware acceleration = performance advantageTamer Dallou, Divino Cesar Soares Lucas, Guido Araujo, Lucas Morais, Eduardo Ferreira Barbosa, Michael Frank, Richard Bagley, Raj Sayana. 1 [doi]
• HW acceleration for volumetric applicationsDavid Moloney. 1-19 [doi]
• ARMv8-A next-generation vector architecture for HPCNigel Stephens. 1-31 [doi]
• HBM package integration: Technology trends, challenges and applicationsSuresh Ramalingam. 1-17 [doi]
• LiveSynth: Towards an interactive synthesis flowRafael Trapani Possignolo, Jose Renau. 1 [doi]
• Welcome to 2016 Hot ChipsStefan Rusu. 1-10 [doi]
• Software in Silicon in the Oracle SPARC M7 processorKathirgamar Aingaran, Sumti Jairath, David Lutz. 1-31 [doi]
• 100Gbit/s, 120km, PAM 4 based switch to switch, layer 2 silicon photonics based optical interconnects for datacentersRadhakrishnan Nagarajan, Sudeep Bhoja, Tom Issenhuth. 1-17 [doi]
• ® Core™: New microarchitecture code named skylakeIttai Anati, David Blythe, Jack Doweck, Hong Jiang, Wen-Fu Kao, Julius Mandelblat, Lihu Rappoport, Efraim Rotem, Ahmad Yasin. 1-39 [doi]
• POWER9: Processor for the cognitive eraBrian W. Thompto. 1-19 [doi]