Abstract is missing.
- Trends in High-Performance ProcessorsFred Weber. 3
- Multithreaded Value PredictionNathan Tuck, Dean M. Tullsen. 5-15 [doi]
- Checkpointed Early Load RetirementNevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez. 16-27 [doi]
- Microarchitectural Wire Management for Performance and Power in Partitioned ArchitecturesRajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy. 28-39 [doi]
- A Small, Fast and Low-Power Register File by Bit-PartitioningMasaaki Kondo, Hiroshi Nakamura. 40-49 [doi]
- Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale BusesKrishnan Sundaresan, Nihar R. Mahapatra. 51-60 [doi]
- Distributing the Frontend for Temperature ReductionPedro Chaparro, Grigorios Magklis, José González, Antonio González. 61-70 [doi]
- Performance, Energy, and Thermal Considerations for SMT and CMP ArchitecturesYingmin Li, David Brooks, Zhigang Hu, Kevin Skadron. 71-82 [doi]
- Tapping ZettaRAM:::TM::: for Low-Power Memory SystemsRavi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg. 83-94 [doi]
- An Efficient Programmable 10 Gigabit Ethernet Network Interface CardPaul Willmann, Hyong-youb Kim, Scott Rixner, Vijay S. Pai. 96-107 [doi]
- A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection NetworksJosé Duato, Ian Johnson, Jose Flich, Finbar Naven, Pedro Javier García, Teresa Nachiondo Frinós. 108-119 [doi]
- Exploring the Design Space of Power-Aware Opto-Electronic Networked SystemsXuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai Huang, Paul R. Prucnal. 120-131 [doi]
- Scatter-Add in Data Parallel ArchitecturesJung Ho Ahn, Mattan Erez, William J. Dally. 132-142 [doi]
- Software Directed Issue Queue Power ReductionTimothy M. Jones, Michael F. P. O Boyle, Jaume Abella, Antonio González. 144-153 [doi]
- On the Limits of Leakage Power Reduction in CachesYan Meng, Timothy Sherwood, Ryan Kastner. 154-165 [doi]
- Heat Stroke: Power-Density-Based Denial of Service in SMTJahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Carla E. Brodley. 166-177 [doi]
- Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain ProcessorsQiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark. 178-189 [doi]
- Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory InstructionsAamer Jaleel, Bruce L. Jacob. 191-200 [doi]
- A Unified Compressed Memory HierarchyErik G. Hallnor, Steven K. Reinhardt. 201-212 [doi]
- A Performance Comparison of DRAM Memory System Optimizations for SMT ProcessorsZhichun Zhu, Zhao Zhang. 213-224 [doi]
- Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial ApplicationsLawrence Spracklen, Yuan Chou, Santosh G. Abraham. 225-236 [doi]
- Stretching the Limits of Clock-Gating Efficiency in Server-Class ProcessorsHans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler. 238-242 [doi]
- The Soft Error Problem: An Architectural PerspectiveShubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt. 243-247 [doi]
- Chip Multithreading: Opportunities and ChallengesLawrence Spracklen, Santosh G. Abraham. 248-252 [doi]
- Enterprise IT Trends and Implications for Architecture ResearchParthasarathy Ranganathan, Norman P. Jouppi. 253-256 [doi]
- Power Efficient Processor Architecture and The Cell ProcessorH. Peter Hofstee. 258-262 [doi]
- The Future of Computer Architecture Research: An Industrial PerspectiveWen-mei W. Hwu, Sanjay J. Patel. 264
- Characterizing and Comparing Prevailing Simulation TechniquesJoshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, Douglas M. Hawkins. 266-277 [doi]
- Transition Phase Classification and PredictionJeremy Lau, Stefan Schoenmackers, Brad Calder. 278-289 [doi]
- SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production RunsFeng Qin, Shan Lu, Yuanyuan Zhou. 291-302 [doi]
- Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISEMarc L. Corliss, E. Christopher Lewis, Amir Roth. 303-314 [doi]
- Unbounded Transactional MemoryC. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie. 316-327 [doi]
- Improving Multiple-CMP Systems Using Token CoherenceMichael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood. 328-339 [doi]
- Predicting Inter-Thread Cache Contention on a Chip Multi-Processor ArchitectureDhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin. 340-351 [doi]
- SENSS: Security Enhancement to Symmetric Shared Memory MultiprocessorsYoutao Zhang, Lan Gao, Jun Yang, Xiangyu Zhang, Rajiv Gupta. 352-362 [doi]