Abstract is missing.
- Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architecturesEmily R. Blem, Jaikrishnan Menon, Karthikeyan Sankaralingam. 1-12 [doi]
- High-performance and energy-efficient mobile web browsing on big/little systemsYuhao Zhu, Vijay Janapa Reddi. 13-24 [doi]
- Skinflint DRAM system: Minimizing DRAM chip writes for low powerYebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee 0002. 25-34 [doi]
- Enabling distributed generation powered sustainable high-performance data centerChao Li, Ruijin Zhou, Tao Li. 35-46 [doi]
- A group-commit mechanism for ROB-based processors implementing the X86 ISAFurat Afram, Hui Zeng, Kanad Ghose. 47-58 [doi]
- Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branchesMuhammad Umar Farooq, Khubaib, Lizy K. John. 59-70 [doi]
- Two level bulk preload branch predictionJames Bonanno, Adam Collura, Daniel Lipetz, Ulrich Mayer, Brian Prasky, Anthony Saporito. 71-82 [doi]
- RECAP: A region-based cure for the common cold (cache)Jason Zebchuk, Harold W. Cain, Xin Tong, Vijayalakshmi Srinivasan, Andreas Moshovos. 83-94 [doi]
- Navigating heterogeneous processors with market mechanismsMarisabel Guevara, Benjamin Lubin, Benjamin C. Lee. 95-106 [doi]
- Application-to-core mapping policies to reduce memory system interference in multi-core systemsReetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi. 107-118 [doi]
- Improving multi-core performance using mixed-cell cache architectureSamira M. Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, Daniel A. Jimenez. 119-130 [doi]
- ECM: Effective Capacity Maximizer for high-performance compressed cachingSeungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, JungHee Lee, Jongman Kim. 131-142 [doi]
- 3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAMMu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce Jacob. 143-154 [doi]
- Modeling performance variation due to cache sharingAndreas Sandberg, Andreas Sembrant, Erik Hagersten, David Black-Schaffer. 155-166 [doi]
- A novel system architecture for web scale applications using lightweight CPUs and virtualized I/OKshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian. 167-178 [doi]
- Cost effective data center serversRui Hou, Tao Jiang, Liuhang Zhang, Pengfei Qi, Jianbo Dong, Haibin Wang, Xiongli Gu, Shujie Zhang. 179-187 [doi]
- Optimizing Google's warehouse scale computers: The NUMA experienceLingjia Tang, Jason Mars, Xiao Zhang, Robert Hagmann, Robert Hundt, Eric Tune. 188-197 [doi]
- Runnemede: An architecture for Ubiquitous High-Performance ComputingNicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, BenoƮt Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu. 198-209 [doi]
- Exploring high-performance and energy proportional interface for phase change memory systemsZhongqi Li, Ruijin Zhou, Tao Li. 210-221 [doi]
- Coset coding to extend the lifetime of memoryAdam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin. 222-233 [doi]
- 2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variationsJue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi. 234-245 [doi]
- Architecture support for guest-transparent VM protection from untrusted hypervisor and physical attacksYubin Xia, Yutao Liu, Haibo Chen. 246-257 [doi]
- SCRAP: Architecture for signature-based protection from Code Reuse AttacksMehmet Kayaalp, Timothy Schmitt, Junaid Nomani, Dmitry Ponomarev, Nael B. Abu-Ghazaleh. 258-269 [doi]
- Adaptive Reliability Chipkill Correct (ARCC)Xun Jian, Rakesh Kumar. 270-281 [doi]
- Accelerating write by exploiting PCM asymmetriesJianhui Yue, Yifeng Zhu. 282-293 [doi]
- Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processorsNeal Clayton Crago, Omid Azizi, Steven S. Lumetta, Sanjay J. Patel. 294-305 [doi]
- Optimizing virtual machine scheduling in NUMA multicore systemsJia Rao, Kun Wang, Xiaobo Zhou, Cheng-Zhong Xu. 306-317 [doi]
- Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasoundRichard Sampson, Ming Yang, Siyuan Wei, Chaitali Chakrabarti, Thomas F. Wenisch. 318-329 [doi]
- Power-efficient computing for compute-intensive GPGPU applicationsSyed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte. 330-341 [doi]
- Power-performance co-optimization of throughput core architecture using resistive memoryNilanjan Goswami, Bingyi Cao, Tao Li. 342-353 [doi]
- Reducing GPU offload latency via fine-grained CPU-GPU synchronizationDaniel Lustig, Margaret Martonosi. 354-365 [doi]
- Worm-Bubble Flow ControlLizhong Chen, Timothy Mark Pinkston. 366-377 [doi]
- Breaking the on-chip latency barrier using SMARTTushar Krishna, Chia-Hsin Owen Chen, Woo-Cheol Kwon, Li-Shiuan Peh. 378-389 [doi]
- TS-Router: On maximizing the Quality-of-Allocation in the On-Chip NetworkYuan-Ying Chang, Yoshi Shih-Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, Chung-Ta King. 390-399 [doi]
- Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchiesAditya Agrawal, Prabhat Jain, Amin Ansari, Josep Torrellas. 400-411 [doi]
- Warped register file: A power efficient register file for GPGPUsMohammad Abdel-Majeed, Murali Annavaram. 412-423 [doi]
- Disintegrated control for energy-efficient and heterogeneous memory systemsTae Jun Ham, Bharath K. Chelepalli, Neng Xue, Benjamin C. Lee. 424-435 [doi]
- Illusionist: Transforming lightweight cores into aggressive cores on demandAmin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, Scott A. Mahlke. 436-447 [doi]
- ESESC: A fast multicore simulator using Time-Based SamplingEhsan K. Ardestani, Jose Renau. 448-459 [doi]
- How to implement effective prediction and forwarding for fusable dynamic multicore architecturesBehnam Robatmili, Dong Li, Hadi Esmaeilzadeh, Madhu Saravana Sibi Govindan, Aaron Smith, Andrew Putnam, Doug Burger, Stephen W. Keckler. 460-471 [doi]
- Bridging the semantic gap: Emulating biological neuronal behaviors with simple digital neuronsAndrew Nere, Atif Hashmi, Mikko H. Lipasti, Giulio Tononi. 472-483 [doi]
- Layout-conscious random topologies for HPC off-chip interconnectsMichihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova. 484-495 [doi]
- Scaling towards kilo-core processors with asymmetric high-radix topologiesNilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge. 496-507 [doi]
- Energy-efficient interconnect via Router ParkingAhmad Samih, Ren Wang, Anil Krishna, Christian Maciocco, Tsung-Yuan Charlie Tai, Yan Solihin. 508-519 [doi]
- In-network traffic regulation for Transactional MemoryLihang Zhao, Woojin Choi, Lizhong Chen, Jeffrey T. Draper. 520-531 [doi]
- Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scalingTayyeb Mahmood, Soontae Kim, Seokin Hong. 532-541 [doi]
- EnergySmart: Toward energy-efficient manycores for Near-Threshold ComputingUlya R. Karpuzcu, Abhishek A. Sinkar, Nam Sung Kim, Josep Torrellas. 542-553 [doi]
- Rainbow: Efficient memory dependence recording with high replay parallelism for relaxed memory modelXuehai Qian, He Huang, Benjamin Sahelices, Depei Qian. 554-565 [doi]
- High-speed formal verification of heterogeneous coherence hierarchiesJesse G. Beu, Jason A. Poovey, Eric R. Hein, Thomas M. Conte. 566-577 [doi]
- Cache coherence for GPU architecturesInderpreet Singh, Arrvindh Shriraman, Wilson W. L. Fung, Mike O'Connor, Tor M. Aamodt. 578-590 [doi]
- The dual-path execution model for efficient GPU control flowMinsoo Rhu, Mattan Erez. 591-602 [doi]
- A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragmentsYaohua Wang, Shuming Chen, Jianghua Wan, Jiayuan Meng, Kai Zhang, Wei Liu, Xi Ning. 603-614 [doi]
- Tiered-latency DRAM: A low latency and low cost DRAM architectureDonghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu. 615-626 [doi]
- A case for Refresh Pausing in DRAM memory systemsPrashant Nair, Chia-Chen Chou, Moinuddin K. Qureshi. 627-638 [doi]
- MISE: Providing performance predictability and improving fairness in shared main memory systemsLavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu. 639-650 [doi]