Abstract is missing.
- elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAsWuxi Li, Yibo Lin, David Z. Pan. 1-8 [doi]
- Automated Probe Repositioning for On-Die EM MeasurementsBastian Richter, Alexander Wild, Amir Moradi 0001. 1-6 [doi]
- Tensor Methods for Generating Compact Uncertainty Quantification and Deep Learning ModelsChunfeng Cui, Cole Hawkins, Zheng Zhang. 1-6 [doi]
- Tagged Sentential Decision Diagrams: Combining Standard and Zero-suppressed Compression and Trimming RulesLiangda Fang, Biqing Fang, Hai Wan, ZeQi Zheng, Liang Chang, Quan Yu. 1-8 [doi]
- Making the Fault-Tolerance of Emerging Neural Network Accelerators ScalableTao Liu 0023, Wujie Wen. 1-5 [doi]
- WCET Guarantees for Opportunistic Runtime ReconfigurationMarvin Damschen, Lars Bauer, Jörg Henkel. 1-6 [doi]
- LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited PaperWalter Lau Neto, Max Austin, Scott Temple, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon. 1-6 [doi]
- Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine LearningAnthony Agnesina, Etienne Lepercq, Jose Escobedo, Sung Kyu Lim. 1-8 [doi]
- An Agile Precision-Tunable CNN Accelerator based on ReRAMYintao He, Ying Wang 0001, Yongchen Wang, Huawei Li, Xiaowei Li 0001. 1-7 [doi]
- Looking Into the Mirror of Open Source: Invited PaperAndrew B. Kahng. 1-8 [doi]
- 4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAsManupa Karunaratne, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh. 1-8 [doi]
- Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-AccelerationQijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma 0003, Guohao Dai, Robert Quitt, Krste Asanovic, John Wawrzynek. 1-8 [doi]
- Verifying Conformance of Neural Network Models: Invited PaperMonal Narasimhamurthy, Taisa Kushner, Souradeep Dutta, Sriram Sankaranarayanan 0001. 1-8 [doi]
- Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain AccessNimisha Limaye, Abhrajit Sengupta, Mohammed Nabeel, Ozgur Sinanoglu. 1-8 [doi]
- Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited PaperRadhakrishna Sanka, Brian Crites, Jeffrey McDaniel, Philip Brisk, Douglas Densmore. 1-8 [doi]
- VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic BiochipsMengchu Li, Tsun-Ming Tseng, Yanlu Ma, Tsung-Yi Ho, Ulf Schlichtmann. 1-8 [doi]
- SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number GeneratorJungmin Park, Seongjoon Cho, Taejin Lim, Swarup Bhunia, Mark Tehranipoor. 1-8 [doi]
- The Internet of Microfluidic Things: Perspectives on System Architecture and Design Challenges: Invited PaperMohamed Ibrahim, Maria Gorlatova, Krishnendu Chakrabarty. 1-8 [doi]
- Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching OrdersGaurav Rajavendra Reddy, Kareem Madkour, Yiorgos Makris. 1-8 [doi]
- CHASE: A Configurable Hardware-Assisted Security Extension for Real-Time SystemsGhada Dessouky, Shaza Zeitouni, Ahmad Ibrahim 0002, Lucas Davi, Ahmad-Reza Sadeghi. 1-8 [doi]
- Accelerating garbage collection for 3D MLC flash memory with SLC blocksShuai Li, Wei Tong, Jingning Liu, Bing Wu, Yazhi Feng. 1-8 [doi]
- Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural NetworkZhengqi Gao, Jun Tao, Fan Yang 0001, Yangfeng Su, Dian Zhou, Xuan Zeng 0001. 1-8 [doi]
- Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level SynthesisTingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang 0012. 1-6 [doi]
- Towards In-Circuit Tuning of Deep Learning DesignsZhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk. 1-6 [doi]
- Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAsJonas Krautter, Dennis R. E. Gnad, Falk Schellenberg, Amir Moradi 0001, Mehdi Baradaran Tahoori. 1-8 [doi]
- GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network GuidanceKeren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan. 1-8 [doi]
- Exploiting Randomness in Stochastic ComputingPai-Shun Ting, John P. Hayes. 1-6 [doi]
- GenUnlock: An Automated Genetic Algorithm Framework for Unlocking Logic EncryptionHuili Chen, Cheng Fu, Jishen Zhao, Farinaz Koushanfar. 1-8 [doi]
- Zac: Towards Automatic Optimization and Deployment of Quantized Deep Neural Networks on Embedded DevicesQingcheng Xiao, Yun Liang 0001. 1-6 [doi]
- Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip DesignsYu-Hsuan Chang, Hsiang-Ting Wen, Yao-Wen Chang. 1-8 [doi]
- Facilitating Deployment Of A Wafer-Based Analytic Software Using Tensor Methods: Invited PaperLi-C. Wang, Chuanhe Jay Shan, Ahmed Wahba. 1-8 [doi]
- Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited PaperFlorian Lonsing, Karthik Ganesan, Makai Mann, Srinivasa Shashank Nuthakki, Eshan Singh, Mario Srouji, Yahan Yang, Subhasish Mitra, Clark W. Barrett. 1-8 [doi]
- Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive ModelsSiyuan Xu, Benjamin Carrión Schäfer. 1-8 [doi]
- Cloud Columba: Accessible Design Automation Platform for Production and Inspiration: Invited PaperTsun-Ming Tseng, Mengchu Li, Yushen Zhang, Tsung-Yi Ho, Ulf Schlichtmann. 1-6 [doi]
- A Novel Macro Placement Approach based on Simulated Evolution AlgorithmJai-Ming Lin, You-Lun Deng, Ya Chu Yang, Jia-Jian Chen, Yao-Chieh Chen. 1-7 [doi]
- A Uniform Modeling Methodology for Benchmarking DNN AcceleratorsIndranil Palit, Qiuwen Lou, Robert Perricone, Michael T. Niemier, Xiaobo Sharon Hu. 1-7 [doi]
- Flip-flop State Driven Clock Gating: Concept, Design, and MethodologyGyoung-Hwan Hyun, Taewhan Kim. 1-6 [doi]
- Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to RealityGaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, Tyler David Sheaves, Hamid Mahmoodi, Sai Manoj P. D., Houman Homayoun, Setareh Rafatirad, Avesta Sasan. 1-8 [doi]
- Efficient Uncertainty Modeling for System Design via Mixed Integer ProgrammingZichang He, Weilong Cui, Chunfeng Cui, Timothy Sherwood, Zheng Zhang. 1-8 [doi]
- SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level SynthesisMuhammad Yasin, Chongzhi Zhao, Jeyavijayan J. V. Rajendran. 1-4 [doi]
- Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling MethodXiao Shi, Hao Yan, Jiajia Zhang, Qiancun Huang, Longxing Shi, Lei He. 1-8 [doi]
- Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited PaperZheng Zhao, Jiaqi Gu, Zhoufeng Ying, Chenghao Feng, Ray T. Chen, David Z. Pan. 1-7 [doi]
- Clock Gating Synthesis of Netlist with Cyclic Logic PathsYonghwi Kwon, Inhak Han, Youngsoo Shin. 1-6 [doi]
- MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers: Invited PaperDebjyoti Bhattacharjee, Abdullah Ash-Saki, Mahabubul Alam, Anupam Chattopadhyay, Swaroop Ghosh. 1-7 [doi]
- Timing-Aware Fill Insertions with Design-Rule and Density ConstraintsTingshen Lan, Xingquan Li, Jianli Chen, Jun Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao-Wen Chang. 1-8 [doi]
- NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal SimulationsShashank Varshney, Hameedah Sultan, Palkesh Jain, Smruti R. Sarangi. 1-8 [doi]
- Time-Frame Folding: Back to the SequentialityPo-Chun Chien, Jie-Hong R. Jiang. 1-8 [doi]
- 2019 CAD Contest: System-level FPGA Routing with Timing Division Multiplexing TechniqueYu-Hsuan Su, Richard Sun, Pei-Hsin Ho. 1-2 [doi]
- High-performance Hardware Architecture for Tensor Singular Value Decomposition: Invited PaperChunhua Deng, Miao Yin, Xiao-Yang Liu, Xiaodong Wang, Bo Yuan. 1-6 [doi]
- ACG-Engine: An Inference Accelerator for Content Generative Neural NetworksHaobo Xu, Ying Wang 0001, Yujie Wang, Jiajun Li, Bosheng Liu, Yinhe Han. 1-7 [doi]
- The Impact of Emerging Technologies on Architectures and System-level Management: Invited PaperJörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang. 1-6 [doi]
- Embedding Binary Perceptrons in FPGA to improve Area, Power and PerformanceAnkit Wagle, Elham Azari, Sarma B. K. Vrudhula. 1-8 [doi]
- Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic NetworksSiang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang. 1-8 [doi]
- Endurance Enhancement of Multi-Level Cell Phase Change MemoryCheongwon Lee, Youngsoo Song, Youngsoo Shin. 1-8 [doi]
- BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural NetworksKourosh Hakhamaneshi, Nick Werblun, Pieter Abbeel, Vladimir Stojanovic. 1-8 [doi]
- Learning Deep Neural Network Controllers for Dynamical Systems with Safety Guarantees: Invited PaperJyotirmoy V. Deshmukh, James Kapinski, Tomoya Yamaguchi, Danil V. Prokhorov. 1-7 [doi]
- Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA PlatformsSahand Salamat, Behnam Khaleghi, Mohsen Imani, Tajana Rosing. 1-8 [doi]
- SemiHD: Semi-Supervised Learning Using Hyperdimensional ComputingMohsen Imani, Samuel Bosch, Mojan Javaheripi, Bita Darvish Rouhani, Xinyu Wu, Farinaz Koushanfar, Tajana Rosing. 1-8 [doi]
- PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator DesignMaryam Parsa, Aayush Ankit, Amirkoushyar Ziabari, Kaushik Roy 0001. 1-8 [doi]
- Scaling Microfluidics to Complex, Dynamic Protocols: Invited PaperMax Willsey, Ashley P. Stephenson, Chris Takahashi, Bichlien H. Nguyen, Karin Strauss, Luis Ceze. 1-6 [doi]
- The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle CircuitsGiulia Meuli, Mathias Soeken, Earl Campbell, Martin Roetteler, Giovanni De Micheli. 1-8 [doi]
- DATC RDF-2019: Towards a Complete Academic Reference Design FlowJianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo. 1-6 [doi]
- nn-dependability-kit: Engineering Neural Networks for Safety-Critical Autonomous Driving SystemsChih-Hong Cheng, Chung-Hao Huang, Georg Nührenberg. 1-6 [doi]
- Understanding and Exploiting the Internals of GPU Resource Allocation for Critical SystemsAlejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Francisco J. Cazorla, Peio Onaindia. 1-8 [doi]
- IcySAT: Improved SAT-based Attacks on Cyclic Locked CircuitsKaveh Shamsi, David Z. Pan, Yier Jin. 1-7 [doi]
- Analyzing and Modeling In-Storage Computing Workloads On EISC - An FPGA-Based System-Level Emulation PlatformZhenyuan Ruan, Tong He, Jason Cong. 1-8 [doi]
- A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded InductorsHakki Mert Torun, Huan Yu, Nihar Dasari, Venkata Chaitanya Krishna Chekuri, Arvind Singh, Jinwoo Kim, Sung Kyu Lim, Saibal Mukhopadhyay, Madhavan Swaminathan. 1-8 [doi]
- Multiversion Concurrency Control on Intermittent SystemsWei-Ming Chen, Yi-Ting Chen, Pi-Cheng Hsiu, Tei-Wei Kuo. 1-8 [doi]
- Towards Verification-Aware Knowledge Distillation for Neural-Network Controlled Systems: Invited PaperJiameng Fan, Chao Huang, Wenchao Li, Xin Chen, Qi Zhu 0002. 1-8 [doi]
- Overview of 2019 CAD Contest at ICCADUlf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin. 1-2 [doi]
- Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited PaperTsun-Ming Tseng, Alexandre Truppel, Mengchu Li, Mahdi Nikdast, Ulf Schlichtmann. 1-6 [doi]
- Global Interconnect OptimizationSiad Daboul, Stephan Held, Bento Natura, Daniel Rotter. 1-8 [doi]
- How to Obtain and Run Light and Efficient Deep Learning NetworksFan Chen, Wei Wen, Linghao Song, Jingchi Zhang, Hai Helen Li, Yiran Chen. 1-5 [doi]
- Strengthening PUFs using CompositionZhuanhao Wu, Hiren D. Patel, Manoj Sachdev, Mahesh V. Tripunitara. 1-8 [doi]
- An Event-driven Neuromorphic System with Biologically Plausible Temporal DynamicsHaowen Fang, Amar Shrestha, Ziyi Zhao, Yilan Li, Qinru Qiu. 1-8 [doi]
- 2019 CAD Contest: LEF/DEF Based Global RoutingSergei Dolgov, Alexander Volkov, Lutong Wang, Bangqi Xu. 1-4 [doi]
- Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAsJianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang. 1-8 [doi]
- What You Simulate Is What You Synthesize: Designing a Processor Core from C++ SpecificationsSimon Rokicki, Davide Pala, Joseph Paturel, Olivier Sentieys. 1-8 [doi]
- Tucker Tensor Decomposition on FPGAKaiqi Zhang, Xiyuan Zhang, Zheng Zhang. 1-8 [doi]
- Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator DesignsYannan Nellie Wu, Joel S. Emer, Vivienne Sze. 1-8 [doi]
- Power-Driven DNN Dataflow Optimization on FPGAQi Sun, Tinghuan Chen, Jin Miao, Bei Yu 0001. 1-7 [doi]
- Re-Tangle: A ReRAM-based Processing-in-Memory Architecture for Transaction-based BlockchainQian Wang, Tianyu Wang, Zhaoyan Shen, Zhiping Jia, Mengying Zhao, Zili Shao. 1-8 [doi]
- Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient EncryptionYi Cai, Xiaoming Chen 0003, Lu Tian, Yu Wang 0002, Huazhong Yang. 1-8 [doi]
- eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN AcceleratorsYoungbeom Jung, YeongJae Choi, Jaehyeong Sim, Lee-Sup Kim. 1-8 [doi]
- MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited PaperBiying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan. 1-8 [doi]
- Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack ProtectionPatanjali SLPSK, Prasanna Karthik Vairam, Chester Rebeiro, V. Kamakoti. 1-8 [doi]
- Adar: Adversarial Activity Recognition in WearablesRamesh Kumar Sah, Hassan Ghasemzadeh. 1-8 [doi]
- MAGNet: A Modular Accelerator Generator for Neural NetworksRangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany. 1-8 [doi]
- ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise OperationsShaahin Angizi, Deliang Fan. 1-8 [doi]
- Power Grid Fixing for Electromigration-induced Voltage FailuresZahi Moudallal, Valeriy Sukharev, Farid N. Najm. 1-8 [doi]
- INA: Incremental Network Approximation Algorithm for Limited Precision Deep Neural NetworksZheyu Liu, Kaige Jia, Weiqiang Liu, Qi Wei 0001, Fei Qiao, Huazhong Yang. 1-7 [doi]
- SPRoute: A Scalable Parallel Negotiation-based Global RouterJiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. 1-8 [doi]
- Towards HDL-based Synthesis of Reversible Circuits with No Additional LinesRobert Wille, Majid Haghparast, Smaran Adarsh, M. Tanmay. 1-7 [doi]
- From Inverse Design to Implementation of Practical PhotonicsJinhie Skarda, Logan Su, Ki Youl Yang, Dries Vercruysse, Neil V. Sapra, Jelena Vuckovic. 1-4 [doi]
- Open-Source Incubation Ecosystem for Digital Microfluidics - Status and Roadmap: Invited PaperXing Huang, Chi-Chun Liang, Jia Li, Tsung-Yi Ho, Chang Jin Kim. 1-6 [doi]
- How to Efficiently Handle Complex Values?: Implementing Decision Diagrams for Quantum ComputingAlwin Zulehner, Stefan Hillmich, Robert Wille. 1-7 [doi]
- A Statistical Timing Model for Low Voltage Design Considering Process VariationPeng Cao 0002, Zhiyuan Liu 0011, Jiangping Wu, Jingjing Guo, Jun Yang 0006, Longxing Shi. 1-8 [doi]
- 2019 CAD Contest: Logic Regression on High Dimensional Boolean SpaceChing-Yi Huang, Chi-An (Rocky) Wu, Tung-Yuan Lee, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo. 1-6 [doi]
- Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA PrototypesAlbert Magyar, David Biancolin, John Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanovic. 1-8 [doi]
- Holistic Power Side-Channel Leakage Assessment: Towards a Robust Multidimensional MetricAlric Althoff, Jeremy Blackstone, Ryan Kastner. 1-8 [doi]
- An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAMKyeonghan Kim, Hyein Shin, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim. 1-8 [doi]
- Multi-Stage Optimization for Energy-Efficient Active Cell Balancing in Battery PacksDebayan Roy, Swaminathan Narayanaswamy, Alma Pröbstl, Samarjit Chakraborty. 1-8 [doi]
- Latest Advancements to the Industry-Leading EPDA Design Flow for Silicon Photonics: Invited PaperJames Pond, Xu Wang, Zeqin Lu, Ellen Schelew, Gilles Lamant, Ahmadreza Farsaei. 1-6 [doi]
- Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule SatisfactionHaocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, Evangeline F. Y. Young. 1-7 [doi]
- SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel AttacksDarshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran. 1-7 [doi]
- Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM DevicesWeidong Cao, Liu Ke, Ayan Chakrabarti, Xuan Zhang. 1-7 [doi]
- GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and OptimizationYi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, Sung Kyu Lim. 1-8 [doi]
- Task Mapping-Assisted Laser Power Scaling for Optical Network-on-ChipsYuyang Wang, Kwang-Ting Cheng. 1-6 [doi]
- Global routing on rhomboidal tilesNicolai Hähnle, Pietro Saccardi. 1-8 [doi]
- HAML-SSD: A Hardware Accelerated Hotness-Aware Machine Learning based SSD ManagementBingzhe Li, Chunhua Deng, Jinfeng Yang, David J. Lilja, Bo Yuan 0001, David H. C. Du. 1-8 [doi]
- A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLSHongzheng Chen, Minghua Shen. 1-8 [doi]
- A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area MinimizationGhasem Pasandi, Massoud Pedram. 1-8 [doi]
- Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage DensityMuhammad Imran, TaeHyun Kwon, Jung Min You, Joon-Sung Yang. 1-7 [doi]
- Mixed Precision Neural Architecture Search for Energy Efficient Deep LearningChengYue Gong, Zixuan Jiang, Dilin Wang, Yibo Lin, Qiang Liu 0001, David Z. Pan. 1-7 [doi]
- ROAD: Improving Reliability of Multi-core System via Asymmetric AgingYu-Guang Chen, Ing-Chao Lin, Jian-Ting Ke. 1-8 [doi]
- ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without RetrainingVojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 1-8 [doi]
- A General Logic Synthesis Framework for Memristor-based Logic DesignZhenhua Zhu, Mingyuan Ma, Jialong Liu, Liying Xu, Xiaoming Chen, Yuchao Yang, Yu Wang, Huazhong Yang. 1-8 [doi]
- NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous DrivingCong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong, Wen-mei Hwu, Junli Gu, Deming Chen. 1-8 [doi]
- IncPIRD: Fast Learning-Based Prediction of Incremental IR DropChia-Tung Ho, Andrew B. Kahng. 1-8 [doi]
- Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection LinesHao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen. 1-6 [doi]
- A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural NetworksHyein Shin, Jaehyeong Sim, Daewoong Lee, Lee-Sup Kim. 1-8 [doi]
- ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous PlatformsKai Lu, Zhaoshi Li, Leibo Liu, Jiawei Wang, Shouyi Yin, Shaojun Wei. 1-8 [doi]
- Toward Instantaneous Sanitization through Disturbance-induced Errors and Recycling Programming over 3D Flash MemoryWei-Chen Wang, Ping-Hsien Lin, Yung-Chun Li, Chien-Chung Ho, Yu-Ming Chang, Yuan-Hao Chang. 1-8 [doi]
- Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for DatacentersZhifei Wang, Jun Feng, Xuanqi Chen, Zhehui Wang, Jiaxu Zhang, Shixi Chen, Jiang Xu 0001. 1-8 [doi]
- Resolving the Trilemma in Logic EncryptionHai Zhou, Amin Rezaei, Yuanqi Shen. 1-8 [doi]
- DEEPEYE: A Deeply Tensor-Compressed Neural Network Hardware Accelerator: Invited PaperYuan Cheng, Guangya Li, Ngai Wong, Hai-Bao Chen, Hao Yu 0001. 1-8 [doi]
- Allocation of State Retention Registers Boosting Practical Applicability to Power Gated CircuitsGyoung-Hwan Hyun, Taewhan Kim. 1-6 [doi]
- FastWave: Accelerating Autoregressive Convolutional Neural Networks on FPGAShehzeen Hussain, Mojan Javaheripi, Paarth Neekhara, Ryan Kastner, Farinaz Koushanfar. 1-8 [doi]
- PURE: Using Verified Remote Attestation to Obtain Proofs of Update, Reset and Erasure in low-End Embedded SystemsIvan De Oliveira Nunes, Karim Eldefrawy, Norrathep Rattanavipanon, Gene Tsudik. 1-8 [doi]
- An All-Digital True Random Number Generator Based on Chaotic Cellular Automata TopologyScott Best, Xiaolin Xu. 1-8 [doi]
- Spec&Check: An Approach to the Building of Shared-Memory Runtime Checkers for Multicore Chip Design VerificationMarleson Graf, Olav P. Henschel, Rafael P. Alevato, Luiz C. V. dos Santos. 1-7 [doi]
- Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-AssemblyZhan-Ling Wang, Yao-Wen Chang. 1-7 [doi]
- Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA SystemsChak-Wa Pui, Evangeline F. Y. Young. 1-8 [doi]