Abstract is missing.
- Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and StreamsMichael Bedford Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman P. Amarasinghe, Anant Agarwal. 2-13 [doi]
- Evaluating the Imagine Stream ArchitectureJung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das. 14-25 [doi]
- Field-testing IMPACT EPIC research results in Itanium 2John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu. 26-39 [doi]
- Wire Delay is Not a Problem for SMT (In the Near Future)T. N. Vijaykumar, Zeshan Chishti. 40-51 [doi]
- The Vector-Thread ArchitectureRonny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic. 52-63 [doi]
- Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload PerformanceRakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas. 64-75 [doi]
- Microarchitecture Optimizations for Exploiting Memory-Level ParallelismYuan Chou, Brian Fahs, Santosh G. Abraham. 76-89 [doi]
- Memory Ordering: A Value-Based ApproachHarold W. Cain, Mikko H. Lipasti. 90-101 [doi]
- Transactional Memory Coherence and ConsistencyLance Hammond, Vicky Wong, Michael K. Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun. 102-113 [doi]
- TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency ModelSudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-Yeu Joseph Lu, Sridhar Narayanan. 114-123 [doi]
- SMTp: An Architecture for Next-generation Scalable Multi-threadingMainak Chaudhuri, Mark Heinrich. 124-137 [doi]
- A Formal Approach to Frequent Energy Adaptations for Multimedia ApplicationsChristopher J. Hughes, Sarita V. Adve. 138-149 [doi]
- Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded ProcessorJohn Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong. 150-161 [doi]
- Power Awareness through Selective Dynamically Optimized TracesRoni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, Avi Mendelson. 162-175 [doi]
- X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDsLakshmi N. Bairavasundaram, Muthian Sivathanu, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau. 176-187 [doi]
- Low-Latency Virtual-Channel Routers for On-Chip NetworksRobert D. Mullins, Andrew West, Simon W. Moore. 188-197 [doi]
- Immunet: A Cheap and Robust Fault-Tolerant Packet Routing MechanismValentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide. 198-211 [doi]
- Adaptive Cache Compression for High-Performance ProcessorsAlaa R. Alameldeen, David A. Wood. 212-223 [doi]
- iWatcher: Efficient Architectural Support for Software DebuggingPin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas. 224-237 [doi]
- From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or SpeculationSami Yehia, Olivier Temam. 238-249 [doi]
- Prophet/Critic Hybrid Branch PredictionAyose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero. 250-263 [doi]
- Techniques to Reduce the Soft Error Rate of a High-Performance MicroprocessorChristopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt. 264-275 [doi]
- The Case for Lifetime Reliability-Aware MicroprocessorsJayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. 276-287 [doi]
- Exploiting Resonant Behavior to Reduce Inductive NoiseMichael D. Powell, T. N. Vijaykumar. 288-301 [doi]
- Use-Based Register Caching with Decoupled IndexingJ. Adam Butts, Gurindar S. Sohi. 302-313 [doi]
- A Content Aware Integer Register File OrganizationRubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero. 314-324 [doi]
- Physical Register InliningMikko H. Lipasti, Brian R. Mestan, Erika Gunadi. 325-337 [doi]
- A First-Order Superscalar Processor ModelTejas Karkhanis, James E. Smith. 338-349 [doi]
- Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design StudiesLieven Eeckhout, Robert H. Bell Jr., Bastiaan Stougie, Koen De Bosschere, Lizy Kurian John. 350-363 [doi]
- Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPsBharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob. 364-375 [doi]
- A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal RedundancyAngshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam. 376-386 [doi]