Table of Contents

• RAIDR: Retention-aware intelligent DRAM refreshJamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu. 1-12 [doi]
• PARDIS: A programmable memory controller for the DDRx interfacing standardsMahdi Nazm Bojnordi, Engin Ipek. 13-24 [doi]
• BOOM: Enabling mobile memory based low-power server DIMMsDoe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan. 25-36 [doi]
• Towards energy-proportional datacenter memory with mobile DRAMKrishna T. Malladi, Frank A. Nothaft, Karthika Periyathambi, Benjamin C. Lee, Christos Kozyrakis, Mark Horowitz. 37-48 [doi]
• Simultaneous branch and warp interweaving for sustained GPU performanceNicolas Brunie, Sylvain Collange, Gregory Frederick Diamos. 49-60 [doi]
• CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architecturesMinsoo Rhu, Mattan Erez. 61-71 [doi]
• iGPU: Exception support and speculative execution on GPUsJaikrishnan Menon, Marc de Kruijf, Karthikeyan Sankaralingam. 72-83 [doi]
• Boosting mobile GPU performance with a decoupled access/execute fragment processorJose-Maria Arnau, Joan-Manuel Parcerisa, Polychronis Xekalakis. 84-93 [doi]
• Branch regulation: Low-overhead protection from code reuse attacksMehmet Kayaalp, Meltem Ozsoy, Nael B. Abu-Ghazaleh, Dmitry Ponomarev. 94-105 [doi]
• Side-channel vulnerability factor: A metric for measuring information leakageJohn Demme, Robert Martin, Adam Waksman, Simha Sethumadhavan. 106-117 [doi]
• TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacksRobert Martin, John Demme, Simha Sethumadhavan. 118-129 [doi]
• Inspection resistant memory: Architectural support for security from physical examinationJonathan Valamehr, Melissa Chase, Seny Kamara, Andrew Putnam, Daniel Shumow, Vinod Vaikuntanathan, Timothy Sherwood. 130-141 [doi]
• Tolerating process variations in nanophotonic on-chip networksYi Xu, Jun Yang 0002, Rami G. Melhem. 142-152 [doi]
• A micro-architectural analysis of switched photonic multi-chip interconnectsPranay Koka, Michael O. McCracken, Herb Schwetman, Chia-Hsin Owen Chen, Xuezhe Zheng, Ron Ho, Kannan Raj, Ashok V. Krishnamoorthy. 153-164 [doi]
• Enhancing effective throughput for transmission line-based busAaron Carpenter, Jianyun Hu, Övünç Kocabas, Michael C. Huang, Hui Wu. 165-176 [doi]
• A case for random shortcut topologies for HPC interconnectsMichihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova. 177-188 [doi]
• Watchdog: Hardware for safe and secure manual memory management and full memory safetySantosh Nagarakatte, Milo M. K. Martin, Steve Zdancewic. 189-200 [doi]
• RADISH: Always-on sound and complete race detection in software and hardwareJoseph Devietti, Benjamin P. Wood, Karin Strauss, Luis Ceze, Dan Grossman, Shaz Qadeer. 201-212 [doi]
• Scheduling heterogeneous multi-cores through performance impact estimation (PIE)Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer. 213-224 [doi]
• The Yin and Yang of power and performance for asymmetric hardware and managed softwareTing Cao, Stephen M. Blackburn, Tiejun Gao, Kathryn S. McKinley. 225-236 [doi]
• Lane decoupling for improving the timing-error resiliency of wide-SIMD architecturesEvgeni Krimer, Patrick Chiang, Mattan Erez. 237-248 [doi]
• VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processorsTimothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu. 249-260 [doi]
• Euripus: A flexible unified hardware memory checkpointing accelerator for bidirectional-debugging and reliabilityIoannis Doudalis, Milos Prvulovic. 261-272 [doi]
• A first-order mechanistic model for architectural vulnerability factorArun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy Kurian John. 273-284 [doi]
• LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systemsAniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi. 285-296 [doi]
• Reducing memory reference energy with opportunistic virtual cachingArkaprava Basu, Mark D. Hill, Michael M. Swift. 297-308 [doi]
• Improving writeback efficiency with decoupled last-write predictionZhe Wang, Samira Manabi Khan, Daniel A. Jiménez. 309-320 [doi]
• FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible ExclusionJaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim. 321-332 [doi]
• Setting an error detection infrastructure with low cost acoustic wave detectorsGaurang Upasani, Xavier Vera, Antonio González. 333-343 [doi]
• Viper: Virtual pipelines for enhanced reliabilityAndrea Pellegrini, Joseph L. Greathouse, Valeria Bertacco. 344-355 [doi]
• A defect-tolerant accelerator for emerging high-performance applicationsOlivier Temam. 356-367 [doi]
• A case for exploiting subarray-level parallelism (SALP) in DRAMYoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu. 368-379 [doi]
• PreSET: Improving performance of phase change memories by exploiting asymmetry in write timesMoinuddin K. Qureshi, Michele Franceschini, Ashish Jagmohan, Luis Lastras. 380-391 [doi]
• Buffer-on-board memory systemsElliott Cooper-Balis, Paul Rosenfeld, Bruce Jacob. 392-403 [doi]
• Physically Addressed Queueing (PAQ): Improving parallelism in Solid State DisksMyoungsoo Jung, Ellis Herbert Wilson, Mahmut T. Kandemir. 404-415 [doi]
• Staged memory scheduling: Achieving high performance and scalability in heterogeneous systemsRachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu. 416-427 [doi]
• Probabilistic Shared Cache Management (PriSM)R. Manikantan, Kaushik Rajan, R. Govindarajan. 428-439 [doi]
• Can traditional programming bridge the Ninja performance gap for parallel computing applications?Nadathur Satish, Changkyu Kim, Jatin Chhugani, Hideki Saito, Rakesh Krishnaiyer, Mikhail Smelyanskiy, Milind Girkar, Pradeep Dubey. 440-451 [doi]
• Harmony: Collection and analysis of parallel block vectorsMelanie Kambadur, Kui Tang, Martha A. Kim. 452-463 [doi]
• Configurable fine-grain protection for multicore processor virtualizationDavid Wentzlaff, Christopher J. Jackson, Patrick Griffin, Anant Agarwal. 464-475 [doi]
• Revisiting hardware-assisted page walks for virtualized systemsJeongseob Ahn, Seongwook Jin, Jaehyuk Huh. 476-487 [doi]
• Managing distributed UPS energy for effective power capping in data centersVasileios Kontorinis, Liuyi Eric Zhang, Baris Aksanli, Jack Sampson, Houman Homayoun, Eddie Pettis, Dean M. Tullsen, Tajana Simunic Rosing. 488-499 [doi]
• Scale-out processorsPejman Lotfi-Kamran, Boris Grot, Michael Ferdman, Stavros Volos, Yusuf Onur Koçberber, Javier Picorel, Almutaz Adileh, Djordje Jevdjic, Sachin Idgunji, Emre Özer, Babak Falsafi. 500-511 [doi]
• iSwitch: Coordinating and optimizing renewable energy powered server clustersChao Li, Amer Qouneh, Tao Li. 512-523 [doi]
• End-to-end sequential consistencyAbhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd D. Millstein, Madanlal Musuvathi. 524-535 [doi]
• BlockChop: Dynamic squash elimination for hybrid processor architectureJason Mars, Naveen Kumar. 536-547 [doi]
• The dynamic granularity memory systemDoe Hyun Yoon, Min Kyu Jeong, Michael Sullivan, Mattan Erez. 548-560 [doi]