Abstract is missing.
- Redundancy-aware Design Space Exploration for Memory Reliability in Many-coresHananeh Aliee, Abbas BanaiyanMofrad, Michael Glaß, Jürgen Teich, Nikil D. Dutt. 1-12
- Containing Guardbands: From the Macro to Micro Time DomainHussam Amrouch, Jörg Henkel. 13-14
- Optimization of a novel WLAN Simulation Framework for Prototyping Network Applications and ProtocolsBenjamin Beichler, Michael Rethfeldt, Hannes Raddatz, Björn Konieczek, Peter Danielis, Christian Haubelt, Dirk Timmermann. 15-26
- Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate ComputingSaman Fröhlich, Daniel Große, Rolf Drechsler. 27-38
- Extending Affine Arithmetic for Formal Verification of Analog/Mixed-Signal SystemsChristoph Grimm 0001, Carna Radojicic. 39-40
- Verifikation von Networked Labs-on-Chip ArchitekturenAndreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille. 41-42
- OpenCL- Design Flow for High Level Synthesis and Cross-Platform PortabilityAmrutansh Gudivada, Daniel Kriesten, Ulrich Heinkel, Rene Röllig, Matthias Lenk. 43-50
- Speculative disassembly of binary codeM. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz. 51-52
- Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint SolvingFelix Neubauer, Karsten Scheibler, Bernd Becker 0001, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer. 53-54
- SystemC AMS based Co-simulation Framework for Cyber Physical SystemsThiyagarajan Purusothaman, Christoph Grimm 0001. 55-66
- Counterexample-Guided EF Synthesis of Boolean FunctionsHeinz Riener, Rüdiger Ehlers, Görschwin Fey. 67-74
- Einfluss von Zellformen auf das Routing von Digital Microfluidic BiochipsLeonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler. 75-78
- Sequential Verification Using Reverse PDRTobias Seufert, Christoph Scholl. 79-90
- Pre-silicon Verification of an Automotive Battery Management System in the Context of the ApplicationSebastian Simon, Jérôme Kirscher, Alexander W. Rath, Zhiqiang Zhang, Linus Maurer. 91-102
- High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common SubcircuitsPatrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf. 103-114
- Towards Timing and Power Analysis of FSM-SADFGs on MPSoCs with Shared Memory CommunicationRalf Stemmer, Maher Fakih. 115-116
- A Novel RTL ATPG Model Based on Gate Inherent Faults of Complex GatesTobias Strauch. 117-128
- Dynamic Power Optimization based on Formal Property Checking of OperationsShrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz. 129-136