Abstract is missing.
- Towards Unifying Localization and Explanation for Automated DebuggingGörschwin Fey, André Sülflow, Rolf Drechsler. 3-8 [doi]
- An Automated Framework for Correction and Debug of PSL AssertionsBrian Keng, Andreas G. Veneris, Sean Safarpour. 9-12 [doi]
- An Efficient Event Generation Method for Testing a SOC with Multiple Processing Elements and Associated PeripheralsDevraj Kallappa Bakchowde, Nanda Kishore A. S.. 15-18 [doi]
- Schedulability Analysis for MultiCore Global Scheduling with Model CheckingWei Sheng, Yanyan Gao, Li Xi, Xuehai Zhou. 21-26 [doi]
- An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability CharacterizationMauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda. 29-34 [doi]
- Automatic Fault Localization for SystemC TLM DesignsHoang M. Le, Daniel Große, Rolf Drechsler. 35-40 [doi]
- A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-ChipOscar Ballan, Paolo Bernardi, Giovanni Fontana, Michelangelo Grosso, Ernesto Sánchez. 43-46 [doi]
- An Embedded Reachability Analyzer and Invariant Checker (ERAIC)Ouiza Dahmoune, Robert de B. Johnston. 47-50 [doi]
- Towards a Multi-MoC Hardware/Software Co-design Framework Using Abstract State MachinesNathan Buchanan, Hiren D. Patel. 53-58 [doi]
- Bounded Model Checking of Incomplete Networks of Timed AutomataChristian Miller, Karina Gitina, Christoph Scholl, Bernd Becker. 61-66 [doi]
- Test Generation for CMP DesignsPadmaraj Singh, David L. Landis. 67-70 [doi]
- Using Graphics Processing Units for Logic Simulation of Electronic DesignsAlper Sen 0001, Baris Aksanli, Murat Bozkurt. 73-76 [doi]