Abstract is missing.
- Architectural Trace-Based Functional Coverage for Multiprocessor VerificationBiruk Mammo, Jim Larimer, Matthew Morgan, Dave Fan, Eric Hennenhoefer, Valeria Bertacco. 1-5 [doi]
- Automatic Formal Correspondence Checking of ISA and RTL Microprocessor DescriptionLuka Charvat, Ales Smrcka, Tomás Vojnar. 6-12 [doi]
- Automatic Generation of On-Line Test Programs through a Cooperation SchemeLyl M. Ciganda, Marco Gaudesi, Evelyne Lutton, Ernesto Sánchez, Giovanni Squillero, Alberto Paolo Tonda. 13-18 [doi]
- Case Study: Verification Framework of Samsung Reconfigurable ProcessorY. Cho, S. Jeong, J. Jeong, H. Shim, Y. Han, S. Ryu, J. Kim. 19-23 [doi]
- Deterministic ATPG for Low Capture Power TestingLung-Jen Lee, Chia-Cheng He, Wang-Dauh Tseng. 24-29 [doi]
- Dual-LFSR Reseeding for Low Power TestingLung-Jen Lee, Wang-Dauh Tseng, Wen-Ting Yang. 30-34 [doi]
- Guaranteeing Termination of Fully Symbolic Timed Forward Model CheckingGeorges Morbé, Christoph Scholl. 35-40 [doi]
- Localization of Bugs in Processor Designs Using zamiaCAD FrameworkAnton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge H. Meza Escobar, Heinz-Dietrich Wuttke. 41-47 [doi]
- New Process to Simultaneously Measure, Quantify, and Model Energy Efficient PerformanceMarkus Mattwandel. 48-53 [doi]
- On the Reuse of RTL IPs for SysML Model GenerationNicola Bombieri, Emad Samuel Malki Ebeid, Franco Fummi, Michele Lora. 54-59 [doi]
- Two-Way Multicasting for Test Data CompressionLung-Jen Lee, Wang-Dauh Tseng, Wei-Shun Chen. 60-64 [doi]
- Verification of CGRA Executable Code and Debugging of Memory Dependence ViolationHeejun Shim, Minwook Ahn, JinSae Jung, Yenjo Han, Soojung Ryu. 65-69 [doi]
- Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon DebugJohnny J. W. Kuan, Tor M. Aamodt. 70-75 [doi]
- Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM SynthesisNicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Sara Vinco. 76-81 [doi]