Abstract is missing.
- Functional Validation of a New Network Switch Architecture Using Rapid Prototyping TechniquesBrian Kahne, Jim Holt. 3-7 [doi]
- Modified Condition Decision Coverage: A Hardware Verification PerspectiveMohamed A. Salem, Kerstin I. Eder. 8-13 [doi]
- Hierarchical Verification Framework for Samsung Reconfigurable Processor Video SystemHoyoung Kim, Seonghun Jeong, Sunmin Kwon, Soojung Ryu. 14-18 [doi]
- Measuring the Gain of Automatic DebugDaniel Hansson, Heli Uronen-Hansson. 19-22 [doi]
- Proving QBF-hardness in Bounded Model Checking for Incomplete DesignsChristian Miller, Christoph Scholl, Bernd Becker. 23-28 [doi]
- Secure and Trusted SoC: Challenges and Emerging SolutionsAbhishek Basak, Sanchita Mal-Sarkar, Swarup Bhunia. 29-34 [doi]
- Practical Security ValidationMatthew L. King. 35-38 [doi]
- Ultra-Fast DMAC TLM Model for High Speed Virtual Platform SimulationMona Safar, Magdy A. El-Moursy, Ashraf Salem. 39-44 [doi]
- Communication Alternatives Exploration in Model-Driven Design of Networked Embedded SystemsEmad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia. 45-51 [doi]
- On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined ProcessorsPaolo Bernardi, R. Cantoro, Lyl M. Ciganda Brasca, B. Du, E. Sanchez, Matteo Sonza Reorda, Michelangelo Grosso, Oscar Ballan. 52-57 [doi]
- IP Testing for Heterogeneous SOCsNarendra Kamat. 58-61 [doi]
- Dynamic Selection of Trace Signals for Post-Silicon DebugKanad Basu, Prabhat Mishra, Priyadarsan Patra, Amir Nahir, Allon Adir. 62-67 [doi]
- Automatic Network Protocol Synthesis from UML Sequence DiagramsEmad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia, Francesco Stefanni. 68-73 [doi]
- Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative ExecutionJack L. Mason, Gregory E. Simco. 74-76 [doi]
- An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication OverheadsTariq Bashir Ahmad, Maciej J. Ciesielski. 77-82 [doi]
- USB Validation Challenges on C45SOI & C28NM Technology ProductsManeesh Kumar Pandey, Atul Gupta, Shwetank Shekhar. 83-88 [doi]
- Anti-counterfeit Techniques: From Design to ResignUjjwal Guin, Domenic Forte, Mohammad Tehranipoor. 89-94 [doi]
- An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoCManeesh Kumar Pandey, Shwetank Shekhar, Nitin Saxena, Gaurav Kumar Agarwal, Amersh Kumar. 95-99 [doi]
- Analyzing Efficacy of Constrained Test Program Generators - A Case StudyVinayak Kamath, Farhan Rahman, Li-C. Wang. 100-105 [doi]
- State Retention Validation of C66X DSP CoreRama Venkatasubramanian, Oluleye Olorode, Abhishek Arun. 106-111 [doi]
- Verification Methodology of Heterogeneous DSP+ARM Multicore Processors for Multi-core System on ChipDavid Brier, Rama Venkatasubramanian, Sowmya Rangarajan, Abhishek Arun, David Thompson, Neelima Muralidharan. 112-117 [doi]