Abstract is missing.
- A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In CalibrationYongsuk Choi, Yong-Bin Kim, In-Seok Jung. 1-5 [doi]
- An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data CorrectionChen Zhang, Gyunam Jeon, Yongsuk Choi, Yong-Bin Kim, Kyung Ki Kim. 6-11 [doi]
- Case Study of Testing a SoC Design with Mixed EDT Channel Sharing and Channel BroadcastingXiao Liu, Changkai Yu, Yu Qi, Yu Huang, James Fu. 12-17 [doi]
- Failures Guide Probabilistic Search for a Hard-to-Find TestMuralidharan Venkatasubramanian, Vishwani D. Agrawal. 18-23 [doi]
- Modeling Residual Life of an IC Considering Multiple Aging MechanismsMd. Nazmul Islam, Sandip Kundu. 24-27 [doi]
- RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMsJoseph Nguyen, David Turgis, David Bonciani, Brice Lhomme, Yann Carminati, Olivier Callen, Guillaume Guirleo, Lorenzo Ciampolini, Gérard Ghibaudo. 28-33 [doi]
- Automated and Reusable IP Functional Test Rule Development across Multiple IP Instances within and across Asic DesignsMalinky Ghosh, Kelly A. Ockunzzi. 34-37 [doi]
- A Tuning Technique for Temperature and Process Variation Compensation of Power Amplifiers with Digital PredistortionHari Chauhan, Vladimir Kvartenko, Marvin Onabajo. 38-45 [doi]
- Using Existing Reconfigurable Logic in 3D Die Stacks for TestFanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter. 46-52 [doi]
- Enabling Debug in IoT Wireless Development and Deployment with Security ConsiderationsAmirhossein Shahshahani, Andrey Tolstikhin, Zeljko Zilic. 53-58 [doi]