Table of Contents

• Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator StartupKim B. Ostman, Erlend Strandvik, Phil Corbishley, Tor Oyvind Vedal, Mika Salmi. 1-4 [doi]
• Low-Power Regulator for Micro Energy Harvesting ApplicationsTapani Nevalainen, Esteban Ferro, Victor M. Brea, Paula López, Ari Paasio. 1-5 [doi]
• Time-Predictable Distributed Shared Memory for Multi-Core ProcessorsMorten B. Petersen, Anthon V. Riber, Simon T. Andersen, Martin Schoeberl. 1-7 [doi]
• An Embedded Programmable Processor for Compressive Sensing ApplicationsMehdi Safarpour, Ilkka Hautala, Olli Silvén. 1-5 [doi]
• Energy-Delay Trade-Offs in Instruction Register File DesignJoonas Multanen, Heikki Kultala, Pekka Jääskeläinen. 1-7 [doi]
• An 87% Peak Efficiency, 37W, Class H Audio Amplifier with GaN Output StageNardi Utomo, Liter Siek, Heng Goh Yap, Don Disney, Lawrence Selvaraj, Lulu Peng. 1-6 [doi]
• A 24GHz, 18dBm, Broadband, Three Stacked Power Amplifier in 28nm FDSOIImad ud Din, Stefan Andersson, Therese Forsberg, Henrik Sjöland. 1-4 [doi]
• Design Considerations and Evaluation of a High-Speed SAR ADCVictor Aberg, Christian Fager, Lars Svensson. 1-6 [doi]
• Multi-Swarm based NoC Configuration and SynthesisMuhammad Obaidullah, Gul N. Khan, Fei Yuan. 1-6 [doi]
• Flying-Capacitor Bottom-Plate Sampling Scheme for Low-Power High-Resolution SAR ADCsDmitry Osipov 0001, Steffen Paul. 1-4 [doi]
• Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride & Logic-Level Power TransistorsJacob E. F. Overgaard, Jens Christian Hertel, Jens Pejtersen, Arnold Knott. 1-6 [doi]
• Current Readout Circuit for Point-of-Care Infectious Disease Diagnostics in Animal HealthKathy Hanley, Aidan Murphy, Niamh Creedon, Alan Or Riordan, Daniel O'Hare, Ivan O'Connell. 1-5 [doi]
• 2, 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical ImplantsArjun Ramaswami Palaniappan, Liter Siek. 1-4 [doi]
• A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCsMustafa Kilic, Selman Ergünay, Yusuf Leblebici. 1-5 [doi]
• A RF Pulse-Width and Pulse-Position Modulator IC in 28 nm FDSOI CMOSMarkus Grozing, Johannes Digel, Thomas Veigel, Robert Bieg, Jianxiong Zhang, Simon Brandl, Martin Schmidt, Christoph Haslach, Daniel Markert, Wolfgang Templ. 1-4 [doi]
• A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta ModulatorsOlaitan Olabode, Vishnu Unnikrishnan, Ilia Kempi, Andreas Hammer, Marko Kosunen, Jussi Ryynänen. 1-4 [doi]
• Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip DesignOliver Schrape, Alexey Balashov, Aleksandar Simevski, Carlos Benito, Milos Krstic. 1-4 [doi]
• VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized AssignmentsMartin Mosbeck, Daniel Hauer, Axel Jantsch. 1-7 [doi]
• Insertion-Loss Optimization of Transformer-based Matching Networks for mm-Wave ApplicationsDavid Bierbuesse, Renato Negra. 1-5 [doi]
• *David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler. 1-6 [doi]
• CMOS photosensors for LIDART. Moradi Khanshan, K. G. Kjeldgard, E. Ulvestad, Dag T. Wisland, Tor Sverre Lande. 1-5 [doi]
• A Design Approach for SiGe Low-Noise Amplifiers Using Wideband Input MatchingZhe Chen, Hao Gao 0001, Peter G. M. Baltus. 1-4 [doi]
• A 15-50GHz Multiplexer Circuit in 130nm SiGe BiCMOS Technology for Ultra-Wide Frequency Ramps in FMCW RadarFrank Herzel, Arzu Ergintav, Johannes Borngräber, Dietmar Kissinger. 1-4 [doi]
• Low-latency Packet Parsing in Software Defined NetworksHesam Zolfaghari, Davide Rossi, Jari Nurmi. 1-6 [doi]
• Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-ChipsAdele Maleki, Hamidreza Ahmadian, Roman Obermaisser. 1-7 [doi]
• Design and Implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore ArchitectureMohammad Ali Pourabed, Sajjad Nouri, Jari Nurmi. 1-6 [doi]
• On Designing PUF-Based TRNGs with Known Answer TestsYang Yu, Elena Dubrova, Mats Näslund, Sha Tao. 1-6 [doi]
• Analysis of Synchronous-Asynchronous NoC for the Dark Silicon EraReem W. Etman, Salma Hesham, Klaus Hoffman, Mohamed A. Abd El ghany, Diana Goehringer. 1-7 [doi]
• A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-EndAyca Akkaya, Firat Celik, Armin Tajalli, Yusuf Leblebici. 1-6 [doi]
• Towards Multidimensional Verification: Where Functional Meets Non-FunctionalMaksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik. 1-7 [doi]
• A Distributed DoS Detection Scheme for NoC-based MPSoCsCesar G. Chaves, Siavoosh Payandeh Azad, Thomas Hollstein, Johanna Sepúlveda. 1-6 [doi]
• Design of Stacked-MOS Transistor mm-Wave Class C Amplifiers for Doherty Power AmplifiersMohammad Hassan Montaseri, Janne Aikio, Timo Rahkonen, Aarno Pärssinen. 1-5 [doi]
• Semiconductor Component Fault Assessment and Probability Impact Estimation on Application LevelJonas Stricker, Clemens Kain, Jérôme Kirscher, Andi Buzo, Linus Maurer, Georg Pelz. 1-4 [doi]
• Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource AllocationElham Shamsa, Anil Kanduri, Amir M. Rahmani, Pasi Liljeberg, Axel Jantsch, Nikil D. Dutt. 1-4 [doi]
• Unleashing the full power of feed-forward opamps: a 200MHz, fully differential, conditionally stable, 36dB gain PGA, using a four-stage multi-path 2.5V amplifier with double feed-forward compensationVahur Kampus, Martin Trojer, Robert Teschner. 1-5 [doi]
• Design and Implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore ArchitectureSajjad Nouri, Ramin Ghaznavi Youvalari, Jari Nurmi. 1-10 [doi]
• Implementation of an Area Efficient Crypto Processor for a NB-IoT SoC PlatformLuis Cavo, Sebastien Fuhrmann, Liang Liu. 1-5 [doi]
• Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence AlignmentRuei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu. 1-5 [doi]
• A Low-Power Hardware Stack for Continuous Data Streaming from Telemetry ImplantsIlia Kempi, Nouman Ahmed, Andreas Hammer, Olaitan Olabode, Vishnu Unnikrishnan, Marko Kosunen, Jussi Ryynänen. 1-6 [doi]
• On Designing PUF-Based TRNGs with Known Answer TestsYang Yu, Elena Dubrova, Mats Näslund, Sha Tao. 1-6 [doi]
• A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOSTherese Forsberg, Johan Wernehag, Henrik Sjöland, Markus Tormanen. 1-4 [doi]
• Dynamically Reconfigurable Gearbox Switched-Capacitor DC-DC ConverterDennis Oland Larsen, Martin Vinter, Ivan H. H. Jørgensen. 1-5 [doi]
• A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform SpectrometerP. Ostrovsky, Oliver Schrape, Klaus Tittelbach-Helmrich, Frank Herzel, G. Fischer, D. Hellmann, P. Borner, A. Loose, P. Hartogh, Dietmar Kissinger. 1-4 [doi]
• GPU-enhanced Multimodal Dense MatchingNicolai Behmann, Max Mehltretter, Sebastian P. Kleinschmidt, Bernardo Wagner, Christian Heipke, Holger Blume. 1-6 [doi]
• Time-gated CMOS SPAD and a Quantum Well Laser Diode with a CMOS Driver for Time-Resolved Diffuse Optics ImagingJan Nissinen, Ilkka Nissinen, S. Jahromi, T. Talala, Juha Kostamovaara. 1-4 [doi]
• Characterization and Considerations for Upset in FPGAChristian Johansson, Torbjorn Manefjord. 1-4 [doi]
• High-speed Sampling System in CMOSE. Ulvestad, Kristian Gjertsen Kjelgard, T. Moradi Khanshan, Dag T. Wisland, Tor Sverre Lande. 1-5 [doi]
• Noise Considerations in Pulse-Shaping Based TIA Channel Designed for a Pulsed TOF Laser Radar ReceiverAram Baharmast, Juha Kostamovaara. 1-6 [doi]
• Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well ProcessMohammad Hassan Montaseri, Risto Vuohtoniemi, Janne Aikio, Timo Rahkonen, Aarno Pärssinen. 1-5 [doi]
• Building Lumped Models for Measured Passive mm-wave ComponentsEero Sankila, Veeti Kiuru, Janne Aikio, Timo Rahkonen. 1-4 [doi]
• Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI TechnologySomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. 1-5 [doi]
• A Comparison of Polar and Quadrature RF-PWMMuhammad Fahim Ul Haque, Muhammad Touqir Pasha, Tahir Malik, Ted Johansson. 1-4 [doi]
• FPGA Based Hybrid Computing Platform for ESS Linac SimulatorArun Jeevaraj, Emmanuel Laface, Maurizio Donna, Fredrik Edman, Liang Liu. 1-4 [doi]