Abstract is missing.
- Sleep-Transistor Based Power-Gating Tradeoff AnalysesSven Rosinger, Wolfgang Nebel. 1-10 [doi]
- Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural LevelChenxi Ni, Ziyad Al Tarawneh, Gordon Russell, Alexandre V. Bystrov. 11-20 [doi]
- Non-invasive Power Simulation at System-Level with SystemCDaniel Lorenz, Philipp A. Hartmann, Kim Grüttner, Wolfgang Nebel. 21-31 [doi]
- A Standard Cell Optimization Method for Near-Threshold Voltage OperationsMasahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera. 32-41 [doi]
- An Extended Metastability Simulation Method for Synchronizer CharacterizationSalomon Beer, Ran Ginosar. 42-51 [doi]
- Phase Space Based NBTI ModelReef Eilers, Malte Metzdorf, Sven Rosinger, Domenik Helms, Wolfgang Nebel. 52-61 [doi]
- Fast Propagation of Hamming and Signal Distances for Register-Transfer Level DatapathsAxel Reimer, Lars Kosmann, Daniel Lorenz, Wolfgang Nebel. 62-71 [doi]
- Noise Margin Based Library Optimization Considering Variability in Sub-thresholdTobias Gemmeke, Maryam Ashouei, Tobias G. Noll. 72-82 [doi]
- TCP Window Based DVFS for Low Power Network Controller SoCEyal-Itzhak Nave, Ran Ginosar. 83-92 [doi]
- Adaptive Synchronization for DVFS ApplicationsGhaith Tarawneh, Alex Yakovlev. 93-102 [doi]
- Muller C-Element Metastability ContainmentThomas Polzer, Andreas Steininger, Jakob Lechner. 103-112 [doi]
- Low Power Implementation of Trivium Stream CipherJ. M. Mora-Gutiérrez, C. J. Jiménez-Fernández, M. Valencia-Barrero. 113-120 [doi]
- A Generic Architecture for Robust Asynchronous Communication LinksJakob Lechner, Robert Najvirt. 121-130 [doi]
- Direct Statistical Simulation of Timing Properties in Sequential CircuitsJavier Rodríguez, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs. 131-141 [doi]
- PVTA Tolerant Self-adaptive Clock Generation ArchitectureJordi Perez-Puigdemont, Antonio Calomarde, Francesc Moll. 142-154 [doi]
- On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor ArchitectureHossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. 155-165 [doi]
- Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline ApplicationsJuan Núñez, Maria J. Avedillo, José M. Quintana. 166-174 [doi]
- Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power MicroprocessorPieter Weckx, Nele Reynders, Ilse de Moffarts, Wim Dehaene. 175-184 [doi]
- Run-Time Measurement of Harvested Energy for Autarkic Sensor OperationDimitris Bekiaris, Ioannis Kosmadakis, George I. Stassinopoulos, Dimitrios Soudris, Theodore Laopoulos, Gregory Doumenis, Stylianos Siskos. 185-193 [doi]
- Low-Power Delay Sensors on FPGAsPanagiotis Sakellariou, Vassilis Paliouras. 194-204 [doi]
- Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous PipelinesArash Saifhashemi, Peter A. Beerel. 205-214 [doi]
- Dynamic Power Management of a Computer with Self Power-Managed ComponentsMaryam Triki, Yanzhi Wang, Ahmed C. Ammari, Massoud Pedram. 215-224 [doi]
- Network Time Synchronization: A Full Hardware ApproachJorge Juan, Julian Viejo, Manuel J. Bellido. 225-234 [doi]
- Case Studies of Logical Computation on Stochastic Bit StreamsPeng Li, Weikang Qian, David J. Lilja, Kia Bazargan, Marc D. Riedel. 235-244 [doi]
- dRail: A Novel Physical Layout Methodology for Power Gated CircuitsJatin N. Mistry, John Biggs, James Myers, Bashir M. Al-Hashimi, David Flynn. 245-255 [doi]