Abstract is missing.
- A Self-Reconfigurable Multimedia Player on FPGAJavier Castillo, Pablo Huerta, César Pedraza, José Ignacio Martínez. 6-11 [doi]
- Reconfigurable Microkernel-based RTOS: Mechanisms and Methods for Run-Time ReconfigurationMarcelo Götz, Florian Dittmann. 12-19 [doi]
- Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array ArchitecturesMarcos Vinícius da Silva, Ricardo S. Ferreira, Alisson Garcia, João M. P. Cardoso. 20-29 [doi]
- A Reconfigurable Simulation Framework for Financial ComputationJacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer. 30-38 [doi]
- A Block-Based Open Source Approach for a Reconfigurable Virtual Instrumentation Platform Using FPGA TechnologyAndres Cicuttin, Maria Liz Crespo, Alexander Shapiro, Nizar Abdallah. 39-46 [doi]
- FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded SystemsSumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst. 47-55 [doi]
- Communication Interface Generation For HW/SW Architecture In The STARSoC EnvironmentAbdelHalim Samahi, El-Bay Bourennane, Sami Boukhechem. 58-63 [doi]
- Executing Algorithms for Dynamic Dataflow Reconfigurable Hardware -The Operators ProtocolJorge Luiz e Silva, Eduardo Marques. 64-70 [doi]
- Tuning Coarse-Grained Reconfigurable Architectures towards an Application DomainJulio A. de Oliveira Filho, Thomas Schweizer, Tobias Oppold, Tommy Kuhn, Wolfgang Rosenstiel. 71-77 [doi]
- Exploring Non-Traditional Hardware-Software InteractionJorge Alberto Surís, Peter M. Athanas. 78-85 [doi]
- A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration OverheadHeng Tan, Ronald F. DeMara. 86-90 [doi]
- Preliminary Steps Towards Protein Folding Prediction Using Reconfigurable ComputingNilton B. Armstrong, Heitor S. Lopes, Carlos R. Erig Lima. 92-98 [doi]
- Implementation of a Parallel Algorithm for Protein Pairwise Alignment Using Reconfigurable ComputingGuilherme L. Moritz, Cristiano Jory, Heitor S. Lopes, Carlos R. Erig Lima. 99-105 [doi]
- Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable HardwareRashad S. Oreifej, Carthik A. Sharma, Ronald F. DeMara. 106-113 [doi]
- Digital Hardware Architectures of Kohonen's Self Organizing Feature Maps with Exponential Neighboring FunctionJorge Peña, Mauricio Vanegas, Andrés Valencia. 114-121 [doi]
- Bio - Inspired & Traditional Approaches to Obtain Fault ToleranceCarlos E. Gutiérrez Salmeron, Andrés David García García, Reynaldo Félix Acuña. 122-129 [doi]
- A QCA Implementation of a Configurable Logic Block for an FPGATimothy Lantz, Eric Peskin. 132-141 [doi]
- Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable ArchitecturesAmeet Chavan, Gaurav Dukle, Ben Graniello, Eric MacDonald. 142-148 [doi]
- Measuring Leakage Power in Nanometer CMOS 6T-SRAM CellsMarcos R. de Alba-Rosano, Andrés David García García. 149-155 [doi]
- 4m) Inverter and its Application in a Reconfigurable Tate Pairing ProcessorMaurice Keller, Robert Ronan, William P. Marnane, Colin C. Murphy. 158-167 [doi]
- An FPGA Implementation of the LMS Adaptive Filter for Audio ProcessingAhmed Elhossini, Shawki Areibi, Robert Dony. 168-175 [doi]
- m) Arithmetic Modules for Elliptic Curve CryptographyMiguel Morales-Sandoval, Claudia Feregrino Uribe. 176-183 [doi]
- Design Space Exploration for an Adaptive Noise Cancellation AlgorithmElvira Martínez de Icaya, Victoria Rodellar, Coral Gonzalez-Concejero, Virginia Peinado, Vicente Angel García-Alcantara. 184-190 [doi]
- Decision Tree Based FPGA-Architecture for Texture Sea State ClassificationSantos López-Estrada, René Cumplido. 191-197 [doi]
- Realization of the sound space environment for the radiation-tolerant space craftHiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga. 198-205 [doi]
- Reconfigurable Implementation of Wavelet Integer Lifting Transforms for Image CompressionSteven Bishop, Suresh Rai, Bahadir K. Gunturk, Jerry L. Trahan, Ramachandran Vaidyanathan. 208-216 [doi]
- Real Time FPGA-based Architecture for Video ApplicationsGriselda Saldaña, Miguel Arias-Estrada. 217-226 [doi]
- FPGA-based Pipeline Architecture to Transform Cartesian Images into Foveal Images by Using a new Foveation ApproachJosé Martínez, Leopoldo Altamirano Robles. 227-236 [doi]
- Change-driven Image Architecture on FPGA with adaptive threshold for Optical-Flow ComputationJulio C. Sosa, Rocío Gómez-Fabela, Jose Antonio Boluda, Fernando Pardo. 237-243 [doi]
- Robust cDNA microarray image processing on a hand-held devicePedro Gómez Vilda, Francisco Díaz Pérez, Bogdan Belean, Raul Malutan, Benjamin Stetter, Rafael Martínez, Victoria Rodellar. 244-248 [doi]
- Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA MacrosThorsten von Sydow, Matthias Korb, Bernd Neumann, Holger Blume, Tobias G. Noll. 252-261 [doi]
- Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPIManuel Saldaña, Daniel Nunes, Emanuel Ramalho, Paul Chow. 260-279 [doi]
- Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous ArchitectureFlorian Dittmann, Achim Rettberg, Raphael Weber. 262-269 [doi]
- Datapath and ISA Customization for Soft VLIW ProcessorsMazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl. 280-289 [doi]
- Implementation, Simulation and Validation of Dispatching Algorithms for Elevator SystemsDaniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón, Rudi H. van Els. 290-297 [doi]
- 8-bit CISC Microprocessor Core for Teaching Applications in the Digital Systems LaboratoryRené de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jose Alberto Vite-Frias, Arturo Garcia-Perez. 300-303 [doi]
- FPGA-Based Educational Platform for Wireless Transmission Using System GeneratorGerardo Eli Martínez-Torres, J. M. Luna-Rivera, Raul E. Balderas-Navarro. 304-313 [doi]
- An FPGA Implementation of Linear Kernel Support Vector MachinesOmar Piña-Ramirez, Raquel Valdés-Cristerna, Oscar Yáñez-Suárez. 314-319 [doi]
- Implementation of Simulation Algorithms in FPGA for Real Time Simulation of Electrical Networks with Power Electronics DevicesJulio C. G. Pimentel. 320-327 [doi]
- High Performance Power Spectrum Analysis Using a FPGA Based Reconfigurable Computing PlatformYogindra Abhyankar, C. Sajish, Yogesh Agarwal, C. R. Subrahmanya, Peeyush Prasad. 328-331 [doi]
- VHDL Core for the Computation of the One-Dimensional Discrete Cosine TransformUlises S. Mendoza-Camarena, René de Jesús Romero-Troncoso. 332-339 [doi]