Table of Contents

• Reconfigurable PDA for the Visually Impaired Using FPGAsXuan Zhang, Cesar Ortega-Sanchez, Iain Murray. 1-6 [doi]
• Embedded Harmonic Control for Trajectory Planning in Large EnvironmentsCesar Torres-Huitzil, Bernard Girau, Amine M. Boumaza, Bruno Scherrer. 7-12 [doi]
• Flexible Architecture for Three Classes of Optical Flow Extraction AlgorithmsJose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Mauricio Cerda. 13-18 [doi]
• Automatic Synthesis of Multiprocessor Systems from Parallel Programs under Preemptive SchedulingHarold Ishebabi, Philipp Mahr, Christophe Bobda. 19-24 [doi]
• Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAsXiaofang Wang, Swetha Thota. 25-30 [doi]
• Automatic Instruction-Set Extensions with the Linear Complexity Spiral SearchCarlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuws, Koen Bertels. 31-36 [doi]
• A Real-Time Embedded System for Stereo Vision Preprocessing Using an FPGAAnders Kjaer-Nielsen, Lars Baunegaard With Jensen, Anders Stengaard Sorensen, Norbert Krüger. 37-42 [doi]
• Finite Precision Analysis of the 3GPP Standard Turbo Decoder for Fixed-Point Implementation in FPGA DevicesAnabel Morales-Cortes, Ramon Parra-Michel, Luis F. Gonzalez-Perez, Gabriela Cervantes T.. 43-48 [doi]
• Parallel Processor for 3D Recovery from Optical FlowJose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel Arias-Estrada. 49-54 [doi]
• A Reconfigurable Platform for Frequent Pattern MiningSong Sun, Michael Steffen, Joseph Zambreno. 55-60 [doi]
• A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable ResourcesJean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, E. Huck, Benoit Miramond, François Verdier, Daniel Chillet, Sébastien Pillement. 61-66 [doi]
• Optimizing Partial Reconfiguration of Multi-context ArchitecturesSven Eisenhardt, Tobias Oppold, Thomas Schweizer, Wolfgang Rosenstiel. 67-72 [doi]
• Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGAYi-Hua E. Yang, Viktor K. Prasanna. 73-78 [doi]
• A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking SystemsJuan Antonio Clemente, Carlos Gonzalez, Javier Resano, Daniel Mozos. 79-84 [doi]
• Optimized Architectural Synthesis of Fixed-Point DatapathsGabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz. 85-90 [doi]
• Developing an MMX Extension for the MicroBlaze Soft ProcessorManuel Hernandez Calvino, Sergio Ruben Geninatti, Jose Ignacio Benavides Benitez. 91-96 [doi]
• An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable ArchitecturesFrancesco Redaelli, Marco D. Santambrogio, Seda Ogrenci Memik. 97-102 [doi]
• Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal TransformsRafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez. 103-108 [doi]
• A Reconfiguration-Aware Floorplacer for FPGAsAlessio Montone, Francesco Redaelli, Marco D. Santambrogio, Seda Ogrenci Memik. 109-114 [doi]
• The Effect of LUT and Cluster Size on a Tree Based FPGA ArchitectureUmer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez. 115-120 [doi]
• Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAsHusain Parvez, Zied Marrakchi, Habib Mehrez. 121-126 [doi]
• Integrating Logic Analyzer Functionality into VHDL DesignsGünter Knittel, Stefanie Mayer, Christian Rothländer. 127-132 [doi]
• Loop Transformations to Reduce the Dynamic FPGA Recon?guration OverheadTom Degryse, Karel Bruneel, Harald Devos, Dirk Stroobandt. 133-138 [doi]
• Leveraging Firmware in Multichip Systems to Maximize FPGA Resources: An Application of Self-Partial ReconfigurationJuan Galindo, Eric Peskin, Brad Larson, Gene Roylance. 139-144 [doi]
• Finite Domain Constraints Based Delay Aware Placement Tool for FPOAsRohit Saraswat, Brandon Eames. 145-150 [doi]
• Arithmetic Operations and Their Energy Consumption in the Nios II Embedded ProcessorDavid M. Cambre, Eduardo I. Boemo, Elias Todorovich. 151-156 [doi]
• Operating System for Symmetric Multiprocessors on FPGAPablo Huerta, Javier Castillo, Carlos Sanchez, José Ignacio Martínez. 157-162 [doi]
• Dynamically Reconfigurable Split Cache ArchitectureLuiza M. N. Coutinho, José Leandro D. Mendes, Carlos A. P. S. Martins. 163-168 [doi]
• Configurable-System-on-Programmable-Chip for Power Electronics Control ApplicationsArmando Astarloa, Unai Bidarte, Jesús Lázaro, Jon Andreu, José Luis Martín. 169-174 [doi]
• Parallel Backprojector for Cone-Beam Computer TomographyNikolay Sorokin. 175-180 [doi]
• Key Research Issues for Reconfigurable Network-on-ChipR. Dafali, Jean-Philippe Diguet, M. Sevaux. 181-186 [doi]
• SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-ChipsPhilipp Mahr, Christian Lorchner, Harold Ishebabi, Christophe Bobda. 187-192 [doi]
• Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoCZ. Jian Jia, Tomás Bautista, Antonio Núñez, Cayetano Guerra, Mario Hernández. 193-198 [doi]
• Part-E - A Tool for Reconfigurable System DesignElmar Weber, Florian Dittmann, Norma Montealegre. 199-204 [doi]
• VIS2SOUND on Reconfigurable HardwareChristian A. Morillas, Juan Pedro Cobos, Francisco J. Pelayo, Alberto Prieto, S. Romero. 205-210 [doi]
• A Fast Emulation-Based NoC Prototyping FrameworkYana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo. 211-216 [doi]
• Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia DevicesSohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello. 217-222 [doi]
• Reconfigurability-Aware Structural Mapping for LUT-Based FPGAsKarel Bruneel, Dirk Stroobandt. 223-228 [doi]
• Fast Implementation of a Bio-inspired Model for Decentralized GatheringBernard Girau, Cesar Torres-Huitzil. 229-234 [doi]
• Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoCDiego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres. 235-240 [doi]
• A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature DescriptorsLars Baunegaard With Jensen, Anders Kjaer-Nielsen, Javier Diaz Alonso, Eduardo Ros, Norbert Krüger. 241-246 [doi]
• Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable ProcessorYuken Kishimoto, Shinichiro Haruyama, Hideharu Amano. 247-252 [doi]
• Dynamic Self-Rescheduling of Tasks over a Heterogeneous PlatformAlécio Pedro Delazari Binotto, Edison Pignaton de Freitas, Marcelo Götz, Carlos Eduardo Pereira, André Stork, Tony Larsson. 253-258 [doi]
• Sequence Alignment with Traceback on Reconfigurable HardwareScott Lloyd, Quinn Snell. 259-264 [doi]
• A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPIManuel Saldaña, Emanuel Ramalho, Paul Chow. 265-270 [doi]
• FPGA Implementation of Pseudo Random Number Generators for Monte Carlo Methods in Quantitative FinanceSimon Banks, Philip Beadling, Andras Ferencz. 271-276 [doi]
• A Pthreads-Based MPI-1 Implementation for MMU-Less MachinesJuan A. Rico-Gallego, Jesús M. Álvarez Llorente, Francisco J. Perogil-Duque, Pedro P. Antunez-Gomez, Juan Carlos Díaz Martín. 277-282 [doi]
• A Hardware Filesystem Implementation for High-Speed Secondary StorageAshwin A. Mendon, Ron Sass. 283-288 [doi]
• A Real-Time FPGA Based Platform for Applications in MechatronicsRoque A. Osornio-Rios, René de Jesús Romero-Troncoso, Luis Morales-Velazquez, J. Jesus de Santiago-Perez, Jesus Rooney Rivera-Guillen, Jose de Jesus Rangel-Magdaleno. 289-294 [doi]
• Disparity Map Hardware AcceleratorHumberto Calderon, Jesús Ortiz, Jean-Guy Fontaine. 295-300 [doi]
• A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware ArchitecturesAbdulhadi Shoufan, Sorin A. Huss, Oliver Kelm, Sebastian Schipp. 301-306 [doi]
• A Temporal Partitioning Methodology for Reconfigurable High Performance ComputersPaulo Sérgio Brandão do Nascimento, Victor W. C. de Medeiros, Viviane Lucy Santos de Souza, Abner Correa Barros, Manoel Eusebio de Lima. 307-312 [doi]
• Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAsSyed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres. 313-318 [doi]
• Reconfigurable Cell Architecture for Systolic and Pipelined Computing DatapathsAbdulrahman Hanoun, Friedrich Mayer-Lindenberg, Bassel Soudan. 319-324 [doi]
• Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAsBin Zhou, David Hwang. 325-330 [doi]
• Generalised Parallel Bilinear Interpolation Architecture for Vision SystemsSuhaib A. Fahmy. 331-336 [doi]
• An FFT/IFFT Design versus Altera and Xilinx CoresC. Gonzalez-Concejero, Victoria Rodellar, Agustín Álvarez Marquina, Elvira Martínez de Icaya, Pedro Gómez Vilda. 337-342 [doi]
• Using a CSP Based Programming Model for Reconfigurable Processor ArraysZain-ul-Abdin, Bertil Svensson. 343-348 [doi]
• A Novel FPGA Implementation of a Wideband Sonar System for Target Motion EstimationSheng Cheng, Chien-Hsun Tseng, Marina Cole. 349-354 [doi]
• Hybrid Architecture for Data-Dependent Superimposed Training in Digital ReceiversFernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo. 355-360 [doi]
• A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP ComponentsRuzica Jevtic, Carlos Carreras, Domenik Helms. 361-366 [doi]
• FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking SystemsJose Juan Garcia Hernandez, Claudia Feregrino Uribe, René Cumplido. 367-372 [doi]
• Universal Wavelet Kernel Implementation Using Reconfigurable HardwareChristophe Desmouliers, Erdal Oruklu, Jafar Saniie. 373-378 [doi]
• Design and Implementation of a Multi-standard Interleaver for 802.11a, 802.11n, 802.16e & DVB StandardsCarlos R. Sanchez-Ortiz, Ramon Parra-Michel, M. E. Guzman-Renteria. 379-384 [doi]
• Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator RingsKnut Wold, Chik-How Tan. 385-390 [doi]
• Parametric, Secure and Compact Implementation of RSA on FPGAErsin Oksuzoglu, Erkay Savas. 391-396 [doi]
• FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m)Ilker Yavuz, Siddika Berna Ors Yalcin, Çetin Kaya Koç. 397-402 [doi]
• Enhanced Correlation Power Analysis Using Key Screening TechniqueToshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki. 403-408 [doi]
• Enhancing an Embedded Processor Core with a Cryptographic Unit for Speed and SecurityOvunc Kocabas, Erkay Savas, Johann Großschädl. 409-414 [doi]
• Triple Rail Logic Robustness against DPAVictor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans. 415-420 [doi]
• FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless NetworksIgnacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval. 421-426 [doi]
• High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA PlatformsMohamed El-Hadedy, Danilo Gligoroski, Svein J. Knapskog. 427-432 [doi]
• Power Consumption Estimations vs Measurements for FPGA-Based Security CoresDimitrios Meintanis, Ioannis Papaefstathiou. 433-437 [doi]
• Celator: A Multi-algorithm Cryptographic Co-processorDaniele Fronte, Annie Pérez, Eric Payrat. 438-443 [doi]
• A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware ImplementationZ. Jezabel Guzman Zavaleta, Claudia Feregrino Uribe, René Cumplido. 444-449 [doi]
• Forward-Secure Content Distribution to Reconfigurable HardwareDavid Champagne, Reouven Elbaz, Catherine H. Gebotys, Lionel Torres, Ruby B. Lee. 450-455 [doi]