Abstract is missing.
- A Minimalistic Architecture for Reconfigurable WFS-Based Immersive-AudioDimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev. 1-6 [doi]
- MARC: A Many-Core Approach to Reconfigurable ComputingIlia A. Lebedev, Shaoyi Cheng, Austin Doupnik, James Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek. 7-12 [doi]
- Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory SpaceOliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker. 13-18 [doi]
- An Efficient Non-blocking Data Cache for Soft ProcessorsKaveh Aasaraai, Andreas Moshovos. 19-24 [doi]
- Runtime Task Mapping Based on Hardware Configuration ReuseKamana Sigdel, Carlo Galuzzi, Koen Bertels, Mark Thompson, Andy D. Pimentel. 25-30 [doi]
- Modeling and Formal Control of Partial Dynamic ReconfigurationSébastien Guillet, Florent de Lamotte, Éric Rutten, Guy Gogniat, Jean-Philippe Diguet. 31-36 [doi]
- Fault Injection Results of Linux Operating on an FPGA Embedded PlatformJoshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings. 37-42 [doi]
- gNOSIS: A Board-Level Debugging and Verification ToolM. Ashfaquzzaman Khan, Richard Neil Pittman, Alessandro Forin. 43-48 [doi]
- Communication Architectures for Run-Time Reconfigurable Modules in a 2-D Mesh on FPGAsJochen Strunk, Johannes Hiltscher, Wolfgang Rehm, Heiko Schick. 49-54 [doi]
- Hardware Particle Swarm Optimization Based on the Attractive-Repulsive Scheme for Embedded ApplicationsDaniel M. Muñoz, Carlos H. Llanos, Leandro dos Santos Coelho, Mauricio Ayala-Rincón. 55-60 [doi]
- FPGA-Based Platform Development for Change Detection in GTAW Welding ProcessRonald H. Hurtado, Sadek C. A. Alfaro, Carlos Humberto Llanos. 61-66 [doi]
- Pruning the Design Space for Just-in-Time Processor CustomizationMariusz Grad, Christian Plessl. 67-72 [doi]
- Applying Model-Checking to Post-Silicon-Verification: Bridging the Specification-Realisation GapOuiza Dahmoune, Robert de B. Johnston. 73-78 [doi]
- A Dynamically Reconfigured Network Platform for High-Speed Malware CollectionSascha Mühlbach, Andreas Koch. 79-84 [doi]
- Design and Implementation of a Visual Fuzzy Control in FPGA for the Ball and Plate SystemMarco A. Moreno-Armendariz, Elsa Rubio, César A. Pérez-Olvera. 85-90 [doi]
- Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable ArchitecturesJosef Angermeier, Stefan Wildermann, E. Sibirko, Jürgen Teich. 91-96 [doi]
- An Application Example of a Run-Time Reconfigurable Embedded SystemDaniel Kriesten, Volker Pankalla, Ulrich Heinkel. 97-102 [doi]
- Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction OperationsMingjie Lin, Shaoyi Cheng, John Wawrzynek. 103-108 [doi]
- UCORE: Reconfigurable Platform for Educational PurposesFrancisco J. Quiles, Manuel Ortiz, María Brox, Carlos D. Moreno, Javier Hormigo, Julio Villalba. 109-114 [doi]
- A Two Level Architecture for High Throughput DCT-Processor and Implementing on FPGAAzad Fakhari, Mahmood Fathy. 115-120 [doi]
- Parallel FPGA-Based Implementation of Recursive Sorting AlgorithmsDmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson. 121-126 [doi]
- Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous CounterpartRui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni. 127-131 [doi]
- Reconfigurable Digital Audio Mixer for Electroacoustic MusicDavid Pedrosa Branco, Iouliia Skliarova, José Vieira. 132-137 [doi]
- A Hardware Architecture of an XML/XPath Broker for Content-Based Publish/Subscribe SystemsFadi El-Hassan, Dan Ionescu. 138-143 [doi]
- A Runtime Profiler: Toward Virtualization of Polymorphic Computing PlatformsHamid Mushtaq, Mojtaba Sabeghi, Koen Bertels. 144-149 [doi]
- Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM)Luis Vitório Cargnini, Yoann Guillemenet, Lionel Torres, Gilles Sassatelli. 150-155 [doi]
- A Novel Hardware Implementation of the Compact Genetic AlgorithmMarco A. Moreno-Armendariz, Nareli Cruz Cortés, Alejandro León-Javier. 156-161 [doi]
- Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor ArchitectureShady O. Agwa, Hany H. Ahmad, Awad I. Saleh. 162-167 [doi]
- Multi-channel Driving Systems for Therapeutic Applications Based-on Focused UltrasoundJ. Pindter-Medina, S. Pichardo, L. Curiel, A. D. Garcia-Garcia, J. E. Chong-Quero. 168-172 [doi]
- Reconfigurable Node Processing Unit for a Low-Power Wireless Sensor NetworkLuis A. Vera-Salas, Sandra V. Moreno-Tapia, Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso. 173-178 [doi]
- Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable HardwareBruno A. Silva, Maurício A. Dias, Jorge L. Silva, Fernando Santos Osório. 179-184 [doi]
- FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio SystemKhaled Sobaihi, Akram Hammoudeh, David Scammell. 185-189 [doi]
- A New Hardware Efficient Inversion Based Random Number Generator for Non-uniform DistributionsChristian de Schryver, Daniel Schmidt 0001, Norbert Wehn, Elke Korn, Henning Marxen, Ralf Korn. 190-195 [doi]
- Performance Analysis of Hardware/Software Middleware in Network of Smart Camera SystemsAli Akbar Zarezadeh, Christophe Bobda. 196-201 [doi]
- Fixed-Point Arithmetic Error Estimation in Monte-Carlo SimulationsXiang Tian, Khaled Benkrid. 202-207 [doi]
- Accelerating 2D FFT with Non-Power-of-Two Problem Size on FPGAWendi Wang, Bo Duan, Chunming Zhang, Peiheng Zhang, Ninghui Sun. 208-213 [doi]
- Parallel Data Sort Using Networked FPGAsJanardhan Singaraju, John A. Chandy. 214-219 [doi]
- Issues on Building an MPI Cluster on MicroblazeJuan Carlos Díaz Martín, Carolina Gómes-Tostón Gutierrez, Alvaro Cortes Facila, Juan A. Rico-Gallego. 220-225 [doi]
- Modeling and Simulation of Reconfigurable Processors in Grid NetworksFaisal Nadeem, Mahmood Ahmadi, Muhammad Nadeem, Stephan Wong. 226-231 [doi]
- Accelerating Texture Features Extraction Algorithms Using FPGA ArchitectureAli Reza Akoushideh, Asadollah Shahbahrami. 232-237 [doi]
- Huffman Coding-Based Compression Unit for Embedded SystemsMarco Antonio Soto Hernandez, Oscar Alvarado Nava, Francisco Javier Zaragoza Martínez. 238-243 [doi]
- FPGA-Based Online Detection of Multiple-Combined Faults through Information Entropy and Neural NetworksEduardo Cabal-Yepez, Ricardo Saucedo-Gallaga, Armando G. Garcia-Ramirez, Arturo A. Fernandez-Jaramillo, Marcos Pena-Anaya, Martin Valtierra-Rodriguez. 244-249 [doi]
- Reconfigurable Cache Implemented on an FPGAA. D. Santana Gil, Jose Ignacio Benavides Benitez, Manuel Hernandez Calviño, E. Herruzo Gomez. 250-255 [doi]
- Hardware Computation of the PageRank EigenvectorSéamas McGettrick, Dermot Geraghty. 256-261 [doi]
- Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions in FPGAsCrina Costea, Florent Bernard, Viktor Fischer, Robert Fouquet. 262-267 [doi]
- Cross-Correlation CartographyLaurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu. 268-273 [doi]
- Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAsShaunak Shah, Rajesh Velegalati, Jens-Peter Kaps, David Hwang. 274-279 [doi]
- HCrypt: A Novel Concept of Crypto-processor with Secured Key ManagementLubos Gaspar, Viktor Fischer, Florent Bernard, Lilian Bossuet, Pascal Cotret. 280-285 [doi]
- High-Speed FPGA-Based Pseudorandom Generators with Extremely Long PeriodsMieczyslaw Jessa, Michal Jaworski. 286-291 [doi]
- Skein Tree Hashing on FPGAAric Schorr, Marcin Lukowiak. 292-297 [doi]
- Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAsYohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh. 298-303 [doi]
- Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete ResultsJulien Francq, Céline Thuillet. 304-309 [doi]
- Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGAZouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley, Hervé Chabanne. 310-315 [doi]
- On FPGA-Based Implementations of the SHA-3 Candidate GrøstlBernhard Jungk, Steffen Reith. 316-321 [doi]
- An Improved GF(2) Matrix Inverter with Linear Time ComplexityRicardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr.. 322-327 [doi]
- Network Processing in Multi-core FPGAs with Integrated Cache-Network InterfaceChristoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis. 328-333 [doi]
- Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable ChipAndrew G. Schmidt, William V. Kritikos, Ron Sass, Erik K. Anderson, Matthew French. 334-339 [doi]
- A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip NetworksAngelo Kuti Lusala, Jean-Didier Legat. 340-345 [doi]
- A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoCNicolas Hebert, Gabriel Marchesan Almeida, Pascal Benoit, Gilles Sassatelli, Lionel Torres. 346-351 [doi]
- Efficient Congestion-Oriented Custom Network-on-Chip Topology SynthesisCristinel Ababei. 352-357 [doi]
- Operating System Structures for Multiprocessor Systems on Programmable ChipMiaoqing Huang, David L. Andrews, Jason Agron. 358-363 [doi]
- Low Power Dual Core MicrocontrollerRajesh Kannan Megalingam, Ashwin Mohan, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Vivek Periye. 364-369 [doi]
- A Process-Oriented Streaming System Design Paradigm for FPGAsLing Liu, Oleksii Morozov. 370-375 [doi]
- R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on ChipLudovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny. 376-381 [doi]
- Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback MechanismGabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. 382-387 [doi]
- Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA PlatformMohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog. 394-399 [doi]
- Singular Value Decomposition Hardware for MIMO: State of the Art and Custom DesignYue Wang, Kevin Cunningham, Prawat Nagvajara, Jeremy Johnson. 400-405 [doi]
- FPGA Implementation of Adjustable Wideband Fractional Delay FIR FiltersG. Ramirez-Conejo, Javier Díaz-Carmona, Agustín Ramírez-Agundis, A. Padilla-Medina, J. Delgado-Frias. 406-411 [doi]
- A Hardware-Efficient Frequency Domain Correlator Architecture for Acquisition Stage in GPSEduardo Romero-Aguirre, Ramon Parra-Michel, Omar Humberto Longoria-Gandara, M. Aguirre-Hernandez. 412-417 [doi]
- Using Partial Reconfiguration in an Embedded Message-Passing SystemManuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow. 418-423 [doi]
- Run-Time Reconfiguration for Automatic Hardware/Software PartitioningTom Davidson, Karel Bruneel, Dirk Stroobandt. 424-429 [doi]
- Configuration Sharing Optimized Placment and RoutingPiotr Stepien, John Cobb. 430-435 [doi]
- Synthesis and Implementation of Hierarchical Finite State Machines with Implicit ModulesValery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson. 436-441 [doi]
- An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching PixelsMichael Schmidt, Dietmar Fey. 442-447 [doi]
- Open Source Precision Timed Soft Processor for Cyber Physical System ApplicationsStephen Craven, Daniel Long, Jason Smith. 448-451 [doi]
- Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD ResolutionHolger Flatt, Holger Blume, Peter Pirsch. 452-457 [doi]
- Flex-SURF: A Flexible Architecture for FPGA-Based Robust Feature Extraction for Optical Tracking SystemsMichael Schaeferling, Gundolf Kiefer. 458-463 [doi]