Table of Contents

• A Composable Workflow for Productive Heterogeneous Computing on FPGAs via Whole-Program Analysis and TransformationPaul Sathre, Ahmed E. Helal, Wu-chun Feng. 1-8 [doi]
• FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCAIevgen Kabin, Dan Kreiser, Zoya Dyka, Peter Langendörfer. 1-7 [doi]
• Language Abstractions for Hardware-based Control-Flow Integrity MonitoringWilliam L. Harrison, Gerard Allwein. 1-6 [doi]
• Complex Multiply Accumulate Cells for the Square Kilometre Array CorrelatorsWilliam Kamp, Norbert Abel, Gianni Comoretto. 1-6 [doi]
• Flexible FPGA ECDSA Design with a Field Multiplier Inherently Resistant against HCCAZoya Dyka, Dan Kreiser, Ievgen Kabin, Peter Langendörfer. 1-6 [doi]
• Post-Routing Analytical Wirelength Model for Homogeneous FPGA ArchitecturesArpit Soni, Yoon Kah Leow, Ali Akoglu. 1-8 [doi]
• Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA DesignsKalindu Herath, Alok Prakash, Guiyuan Jiang, Thambipillai Srikanthan. 1-8 [doi]
• HW/SW Configurable LQG Controller using a Sequential Discrete Kalman FilterMatthew Cauwels, Joseph Zambreno, Phillip H. Jones. 1-8 [doi]
• Design and Fabrication of Full Board Direct Liquid Cooling Heat Sink for Densely Packed FPGA Processing BoardsPaulina Fusiara, Gijs Schoonderbeek, Johan Pragt, Leon Hiemstra, Sjouke Kuindersma, Menno Schuil, Grant Hampson. 1-8 [doi]
• Accelerating Key In-memory Database Functionality with FPGA TechnologyJohn McGlone, Paolo Palazzari, J. B. Leclere. 1-8 [doi]
• A small and adaptive coprocessor for information flow tracking in ARM SoCsMuhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapotre, Guy Gogniat. 1-8 [doi]
• FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps NetworksGustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso. 1-6 [doi]
• A Highly Parallel FPGA Implementation of Sparse Neural Network TrainingSourya Dey, Diandian Chen, Zongyang Li, Souvik Kundu, Kuan-Wen Huang, Keith M. Chugg, Peter A. Beerel. 1-4 [doi]
• Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical SystemsTiziana Fanni, Alfonso Rodriguez, Carlo Sau, Leonardo Suriano, Francesca Palumbo, Luigi Raffo, Eduardo de la Torre. 1-8 [doi]
• AutoStreams: Fully Automatic parallelization of Legacy Embedded Applications with Soft-Core MPSoCsKris Heid, Christian Hochberger. 1-7 [doi]
• High-Level Executable Models of Reactive Real-Time Systems with Logic-Labelled Finite-State Machines and FPGAsVladimir Estivill-Castro, René Hexel, Morgan McColl. 1-8 [doi]
• An FPGA-based Hardware Accelerator for Iris SegmentationJoe Avey, Phillip H. Jones, Joseph Zambreno. 1-8 [doi]
• Evaluating Floating-point Intensive Applications on OpenCL FPGA Platforms: A Case Study on the SimpleMOC KernelZheming Jin, Hal Finkel. 1-6 [doi]
• FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter SearchTakashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka. 1-8 [doi]
• Throughput-Optimized Frequency Domain CNN with Fixed-Point Quantization on FPGAWeiyi Sun, Hanqing Zeng, Yi-Hua Edward Yang, Viktor K. Prasanna. 1-8 [doi]
• Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable ArchitecturesDillon Huff, Pat Hanrahan. 1-6 [doi]
• An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo VisionRyo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri. 1-6 [doi]
• Full-HD Accelerated and Embedded Feature Detection Video System with 63fps using ORB for FREAKLester Kalms, Hassan Ibrahim, Diana Göhringer. 1-6 [doi]
• Exploring FPGA-specific Optimizations for Irregular OpenCL ApplicationsMohamed W. Hassan, Ahmed E. Helal, Peter M. Athanas, Wu-chun Feng, Yasser Y. Hanafy. 1-8 [doi]
• A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flopsTakeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami. 1-6 [doi]
• Configuration Tampering of BRAM-based AES Implementations on FPGAsDaniel Ziener, Jutta Pirkl, Jürgen Teich. 1-7 [doi]
• System Services for Reconfigurable Hardware Acceleration in Mobile DevicesHsin-Yu Ting, Ardalan Amiri Sani, Eli Bozorgzadeh. 1-6 [doi]
• An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNsAhmed M. Abdelsalam, Felix Boulet, Gabriel Demers, J. M. Pierre Langlois, Farida Cheriet. 1-6 [doi]
• Towards a Generalized Reconfigurable Agent-Based Architecture: Stock Market Simulation AccelerationAlan Ehret, Mihailo Isakov, Michel A. Kinsy. 1-6 [doi]
• A Coarse-Grained Reconfigurable Array for High-Performance Computing ApplicationsPhilipp S. Kasgen, Markus Weinhardt, Christian Hochberger. 1-4 [doi]
• Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCsFranz-Josef Streit, Martin Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich. 1-8 [doi]
• LaKe: The Power of In-Network ComputingYuta Tokusashi, Hiroki Matsutani, Noa Zilberman. 1-8 [doi]
• MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAsShuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao. 1-8 [doi]
• High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature SchemeAhmed Ferozpuri, Kris Gaj. 1-8 [doi]
• Experimental Power and Performance Evaluation of CAESAR Hardware FinalistsMichael Tempelmeier, Georg Sigl, Jens-Peter Kaps. 1-6 [doi]
• IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx VivadoRafael Zamacola, Alberto García-Martínez, Javier Mora 0001, Andrés Otero, Eduardo de la Torre. 1-8 [doi]
• Dynamic tunable and reconfigurable hardware controller with EKF-based state reconstruction through FPGA-in the loopGökhan Akgün, Habib ul Hasan Khan, Mahmoud Ahmed Elshimy, Diana Göhringer. 1-8 [doi]
• An Application Specific Framework for HLS-based FPGA Design of Articulated Robot Inverse KinematicsSafdar Mahmood, Pavel Shydlouski, Michael Hubner. 1-6 [doi]
• A Scalable and Low Power DCNN for Multimodal Data ClassificationAli Jafari, Morteza Hosseini, Houman Homayoun, Tinoosh Mohsenin. 1-6 [doi]