Abstract is missing.
- Software Is the Answer But What Is the Question?Willie Anderson. 1 [doi]
- Integrating VLIW Processors with a Network on ChipJos Huisken. 2 [doi]
- Communication Architecture Simulation on the Virtual Synchronization FrameworkTaewook Oh, Youngmin Yi, Soonhoi Ha. 3-12 [doi]
- A Model-Driven Automatically-Retargetable Debug Tool for Embedded SystemsMax R. de O. Schultz, Alexandre K. I. Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. dos Santos. 13-23 [doi]
- Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space ExplorationSangsoo Park, Heonshik Shin. 24-33 [doi]
- SC2SCFL: Automated SystemC to SystemC:::FL::: TranslationKa Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, Michel P. Schellekens. 34-45 [doi]
- Model and Validation of Block Cleaning Cost for Flash MemorySeungjae Baek, Jongmoo Choi, Donghee Lee, Sam H. Noh. 46-54 [doi]
- VLSI Architecture for MRF Based Stereo MatchingSungchan Park, Chao Chen, Hong Jeong. 55-64 [doi]
- Low-Power Twiddle Factor Unit for FFT ComputationTeemu Pitkänen, Tero Partanen, Jarmo Takala. 65-74 [doi]
- Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded MultiprocessorsPepijn J. de Langen, Ben H. H. Juurlink. 75-85 [doi]
- An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded CodeJosé O. Carlomagno Filho, Luiz F. P. Santos, Luiz C. V. dos Santos. 86-95 [doi]
- Improving TriMedia Cache Performance by Profile Guided Code ReorderingNorbert Esser, Renga Sundararajan, Joachim Trescher. 96-106 [doi]
- A Streaming Machine Description and Programming ModelPaul Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé. 107-116 [doi]
- Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via PackingBastian Ristau, Gerhard Fettweis. 117-126 [doi]
- Strategies for Compiling µ TC to Novel Chip MultiprocessorsThomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg. 127-138 [doi]
- Image Quantisation on a Massively Parallel Embedded ProcessorJan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit. 139-148 [doi]
- Stream Image Processing on a Dual-Core Embedded SystemMichael G. Benjamin, David R. Kaeli. 149-158 [doi]
- MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia ProcessingMarco Lanuzza, Stefania Perri, Pasquale Corsonello. 159-168 [doi]
- FPGA Design Methodology for a Wavelet-Based Scalable Video DecoderHendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt. 169-178 [doi]
- Evaluating Large System-on-Chip on Multi-FPGA PlatformAri Kulmala, Erno Salminen, Timo D. Hämäläinen. 179-189 [doi]
- Efficiency Measures for Multimedia SOCsHartwig Jeschke. 190-199 [doi]
- On-Chip Bus Modeling for Power and Performance EstimationJe-Hoon Lee, Young-Sin Cho, Seok-Man Kim, Kyoung-Rok Cho. 200-210 [doi]
- A Framework Introducing Model Reversibility in SoC Design Space ExplorationAlexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frédéric Robert. 211-221 [doi]
- Towards Multi-application Workload Modeling in Sesame for System-Level Design Space ExplorationMark Thompson, Andy D. Pimentel. 222-232 [doi]
- Resource Conflict Detection in Simulation of Function Unit PipelinesPekka Jääskeläinen, Vladimír Guzma, Jarmo Takala. 233-240 [doi]
- A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal ProcessingHolger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch. 241-250 [doi]
- High-Bandwidth Address Generation UnitHumberto Calderon, Carlo Galuzzi, Georgi Gaydadjiev, Stamatis Vassiliadis. 251-262 [doi]
- An IP Core for Embedded Java SystemsSascha Uhrig, Jörg Mische, Theo Ungerer. 263-272 [doi]
- Parallel Memory Architecture for TTA ProcessorJarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala. 273-282 [doi]
- A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable SizeCarlo Galuzzi, Koen Bertels, Stamatis Vassiliadis. 283-293 [doi]
- Automated Power Gating of Registers Using CoDeL and FSM Branch PredictionNainesh Agarwal, Nikitas J. Dimopoulos. 294-303 [doi]
- A Study of Energy Saving in Customizable ProcessorsPaolo Bonzini, Dilek Harmanci, Laura Pozzi. 304-312 [doi]
- Trends in Low Power Handset Software Defined RadioJohn Glossner, Daniel Iancu, Mayan Moudgill, Michael J. Schulte, Stamatis Vassiliadis. 313-321 [doi]
- Design of a Low Power Pre-synchronization ASIP for Multimode SDR TerminalsThomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor. 322-332 [doi]
- Area Efficient Fully Programmable Baseband ProcessorsAnders Nilsson, Dake Liu. 333-342 [doi]
- The Next Generation Challenge for Software Defined RadioMark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner. 343-354 [doi]
- Design Methodology for Software Radio SystemsChia-han Lee, Wayne Wolf. 355-364 [doi]
- Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoCTseesuren Batsuuri, Je-Hoon Lee, Kyoung-Rok Cho. 365-374 [doi]
- A Comparative Study of Different FFT Architectures for Software Defined RadioShashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas. 375-384 [doi]
- Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical MonitoringLennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen. 385-395 [doi]
- Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor NetworkMauri Kuorilehto, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen. 396-407 [doi]
- System Architecture Modeling of an UWB Receiver for Wireless Sensor NetworkAubin Lecointre, Daniela Dragomirescu, Robert Plana. 408-420 [doi]
- An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor NetworksZhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta. 421-430 [doi]
- SensorOS: A New Operating System for Time Critical WSN ApplicationsMauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen. 431-442 [doi]
- Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor NetworksPanu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen. 443-453 [doi]
- :::: k:::: ::: + ::: :::: Neigh:::: : An Energy Efficient Topology Control for Wireless Sensor NetworksDong-Min Son, Young-Bae Ko. 454-463 [doi]