Table of Contents

• Low-power inter-core communication through cache partitioning in embedded multiprocessorsChenjie Yu, Xiangrong Zhou, Peter Petrov. [doi]
• DRAM power management and energy consumption: a critical assessmentDaniel Schmidt 0001, Norbert Wehn. [doi]
• A self-protected integrated switch in a HV technologyMatias Miguez, Alfredo Arnaud, Joel Gak. [doi]
• An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based lockingRaju Halder, Parthasarathi Dasgupta, Saptarshi Naskar, Samar Sen-Sarma. [doi]
• Using NoC routers as processing elementsSílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva. [doi]
• Design of low complexity digital FIR filtersLevent Aksoy, Diego Jaccottet, Eduardo Costa. [doi]
• Zero quiescent current startup circuit with automatic turning-off for low power current and voltage referenceAndre Mansano, Andre Vilas Boas, Alfredo Olmos, Jefferson Soldera. [doi]
• Resource-and-time-aware test strategy for configurable quaternary logic blocksÉrika F. Cota, Luigi Carro, Felipe Pinto, Ricardo Augusto da Luz Reis, Marcelo Lubaszewski. [doi]
• Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdownHagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann. [doi]
• Low-power CMOS transceivers with on-chip antennas for short-range radio-frequency communicationCalvin Plett, Robson Nunes de Lima. [doi]
• A compact fast-response charge-pump gate driverAndré Mansano, Jader A. De Lima, Jacobus Swart. [doi]
• Floating gate MOSFET circuit design for a monolithic MEMS GAS sensorM. Alfredo Reyes-Barranca, S. Mendoza-Acevedo, A. Ávila-García, J. L. González-Vidal, Luis M. Flores-Nava. [doi]
• A methodology for tuning two-level cache hierarchy considering energy and performanceAbel G. Silva-Filho, C. C. Araújo. [doi]
• On the energy-efficiency of software transactional memoryFelipe Klein, Alexandro Baldassin, Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo. [doi]
• Multichannel intracortical neurorecording: integration and packaging challengesMohamad Sawan, Benoit Gosselin. [doi]
• Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologiesRafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías. [doi]
• Fault tolerant mechanism to improve yield in NoCs using a reconfigurable routerCaroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz. [doi]
• CMOS 2.45GHz RF power amplifier for RFID readerM. J. Uddin, Muhammad I. Ibrahimy, M. A. Hasan, Mohd. Alauddin Mohd. Ali, Mamun Bin Ibne Reaz. [doi]
• Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuitsWimol San-Um, Tachibana Masayoshi. [doi]
• Exploiting the model-driven engineering approach to improve design space exploration of embedded systemsMarcio F. da S. Oliveira, Ronaldo R. Ferreira, Francisco Assis M. do Nascimento, Franz J. Rammig, Flávio Rech Wagner. [doi]
• Architecture for dense matrix multiplication on a high-performance reconfigurable systemViviane Lucy Santos de Souza, Victor Wanderley Costa Medeiros, Manoel Eusebio de Lima. [doi]
• System concept for an FPGA based real-time capable automotive ECU simulation systemOliver Sander, Christoph Roth, Vitali Stuckert, Jürgen Becker. [doi]
• Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LOCédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Begueret. [doi]
• A cyborg beetle: wireless neural flight control of a free-flying insectM. M. Maharbiz. [doi]
• Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technologyLuiz Carlos Moreira, Wilhelmus A. M. Van Noije, Armando Ayala Pabón, Andrés Farfán-Peláez. [doi]
• ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networksIgor Dantas dos Santos Miranda, Ana Isabela Araújo Cunha. [doi]
• Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear functionLuciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela A. Cunha. [doi]
• Parameterizable floating-point library for arithmetic operations in FPGAsDiego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón. [doi]
• A high abstraction, high accuracy power estimation model for networks-on-chipLuciano Ost, Guilherme Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp, Fernando Moraes. [doi]
• Functional verification of power gate design in SystemC RTLGeorge Sobral Silveira, Alisson Vasconcelos De Brito, Elmar U. K. Melcher. [doi]
• High performance and low cost architecture for H.264/AVC CAVLD targeting HDTVThaísa Leal da Silva, Fabio Pereira, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini. [doi]
• Reliability aware yield improvement technique for nanotechnology based circuitsCostas Argyrides, G. Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro. [doi]
• Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensorFrank Sill, Davies W. de Lima Monteiro. [doi]
• Improved placement for hierarchical FPGAs exploiting local interconnect resourcesValerij Matrose, Carsten Gremzow. [doi]
• Protecting digital circuits against hold time violation due to process variabilityGustavo Neuberger, Gilson I. Wirth, Ricardo Reis. [doi]
• High performance motion estimation architecture using efficient adder-compressorsAndré Silva, Eduardo A. C. da Costa, Sergio Almeida, Marcelo Schiavon Porto, Sergio Bampi. [doi]
• Transforms and quantization design targeting the H.264/AVC intra prediction constraintsRobson Dornelles, Felipe Sampaio, Daniel Palomino, Luciano Volcan Agostini. [doi]
• Highly improved IIP2 direct conversion receiverAntonio Felipe de Freitas Silva, Fernando Rangel de Sousa. [doi]
• Design and characterization of a 0.35 micron CMOS voltage-to-current converterGenival Mariano de Araujo, Heider Marconi G. Madureira, José Camargo da Costa. [doi]
• BRICK: a multi-context expression grained reconfigurable architectureJuan Fernando Eusse Giraldo, Michael Hübner, Ricardo Pezzuol Jacobi. [doi]
• What about the IP of your IP?: an introduction to intellectual property law for engineers and scientistsAndré Inácio Reis, Roner G. Fabris. [doi]
• A merged RF CMOS LNA-Mixer design using geometric programmingSergio Chaparro, Armando Ayala Pabón, Elkim Roa, Wilhelmus A. M. Van Noije. [doi]
• Adding mechanisms for QoS to a network-on-chipMarcelo Daniel Berejuck, Cesar Albenes Zeferino. [doi]
• An early real-time checker for retargetable compile-time analysisEmilio Wuerges, Luiz C. V. dos Santos, Olinto J. V. Furtado, Sandro Rigo. [doi]
• A low-voltage bandgap reference source based on the current-mode techniqueJuan José Carrillo, Elkim Roa, José Vieira, Wilhelmus A. M. Van Noije. [doi]
• A compact low-distortion low-power instrumentation amplifierJader A. De Lima. [doi]
• Design of an embedded system for the proactive maintenance of electrical valvesLuiz F. Gonçalves, Jefferson L. Bosa, Renato V. B. Henriques, Marcelo Lubaszewski. [doi]
• A PD-based methodology to enhance efficiency in testbenches with random stimulationCarlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau. [doi]
• A novel delta sigma built-in-current-sensor as a signal strength indicator for RF transceiver reconfigurationLaurent Leyssenne, Eric Kerherve, Yann Deval, Didier Belot. [doi]
• A logic built-in self-test architecture that reuses manufacturing compressed scan test patternsDiogo José Costa Alves, Edna Barros. [doi]
• Design validation of multithreaded architectures using concurrent threads evolutionDanilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Giovanni Squillero. [doi]
• A path-load based adaptive routing algorithm for networks-on-chipLeonel Tedesco, Fabien Clermidy, Fernando Moraes. [doi]
• Using MDE for the formal verification of embedded systems modeled by UML sequence diagramsFrancisco Assis M. do Nascimento, Marcio F. da S. Oliveira, Flávio Rech Wagner. [doi]
• Design of a low power MPEG-1 motion vector reconstructorM. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig. [doi]