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Xiangwei Li. Time-multiplexed FPGA overlays with linear interconnect. PhD thesis, Nanyang Technological University, Singapore, 2018. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A time-multiplexed FPGA overlay with linear interconnectXiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy. date 2018: 1075-1080 [doi] High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA OverlayXiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain. iscas 2020: 1-5 [doi]
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