Table of Contents

• Hardware Security in the Internet of Things: A SurveySonia Akter, Kasem Khalil, Magdy A. Bayoumi. 1-6 [doi]
• EvoSh: Evolutionary Search with Shaving to Enable Power-Latency Tradeoff in Deep Learning Computing on Embedded SystemsBasar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey. 1-6 [doi]
• Thermal Integrity of ReRAM-based Near-Memory Computing in 3D Integrated DNN AcceleratorsAbrar Abdurrob, Emre Salman, Jack Lombardi. 1-6 [doi]
• RECS: A Scalable Platform for Heterogeneous ComputingKevin Mika, Florian Porrmann, Nils Kucza, René Griessl, Jens Hagemeyer. 1-6 [doi]
• Vertical Power Delivery for Emerging Packaging and Integration Platforms - Power Conversion and DistributionSriharini Krishnakumar, Inna Partin-Vaisband. 1-6 [doi]
• PRIDES: A Power Rising Descending Signature for Improving IoT SecurityAshish Mahanta, Haibo Wang. 1-6 [doi]
• CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNsChristie Agbalessi, Mark A. Indovina. 1-6 [doi]
• 18FD-SOI: Case Study at ArmPragya Laad. 1-2 [doi]
• Investigation of Communication Overhead of SoC Lookaside AcceleratorsAlperen Bolat, Fahad Siddiqui 0001, Sakir Sezer, Kasim Tasdemir, Rafiullah Khan. 1-6 [doi]
• A Low Latency Spiking Neural Network with Improved Temporal DynamicsYunpeng Yao, Yirong Kan, Guangxian Zhu, Renyuan Zhang. 1-6 [doi]
• DCVS Level Shifter for Clock PathMin-Su Kim, Jin Soo Park, Chung Hee Kim, Bai-Sun Kong. 1-2 [doi]
• On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN AcceleratorsZheyu Yan, Yifan Qin, Xiaobo Sharon Hu, Yiyu Shi 0001. 1-6 [doi]
• Deep Neural Network-Based Accelerators for Repetitive Boolean Logic EvaluationDanushka Senarathna, Spyros Tragoudas. 1-6 [doi]
• Fine-Grained Transistor-Level QDI Asynchronous Crossbar SwitchShahzad Haider, Ke Hu, Song Chen 0001. 1-5 [doi]
• Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-MemoryBen Perach, Ronny Ronen, Shahar Kvatinsky. 1-6 [doi]
• XANDAR: Verification & Validation Approach for Safety-critical SystemsBalmukund Sonigara, Sakir Sezer, Fahad Siddiqui 0001, Raphael Weber, Konstantinos Antonopoulos, Christos Panagiotou, Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Sena Yengec Tasdemir, Henry Hui, Kieran McLaughlin. 1-6 [doi]
• Pin Accessibility Improvement with Hit-Point Distribution Metrics for Sub-4nm Standard CellJaeha Lee, Seungmin Lee, Hyeongkyu Kim, Taejun Yoo, Minjung Park, Seiseung Yoon. 1-6 [doi]
• Thin-Film Memristors and Memcapacitors for 3D Integration of Neuromorphic SystemsMutsumi Kimura, Shu Shiomi, Norito Komai, Etsuko Iwagi, Tomoharu Yokoyama, Yuma Ishisaki, Tokiyoshi Matsuda, Hidenori Kawanishi. 1-6 [doi]
• A Delay and Power Efficient Voltage Level Shifter with Low Leakage PowerMehdi Saberi, Zahra Ghasemzadeh, Alexandre Schmid. 1-5 [doi]
• A Runtime Security Monitoring Architecture for Embedded HypervisorsHenry Hui, Kieran McLaughlin, Fahad Siddiqui 0001, Sakir Sezer, Sena Yengec Tasdemir, Balmukund Sonigara. 1-6 [doi]
• Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy EfficiencyTim Hotfilter, Julian Höfer, Philipp Merz, Fabian Kreß, Fabian Kempf, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• M-Party: A Secure Dynamic Cache Partitioning by More Than Two PartiesYuan-Tai Lin, Chin-Yu Sun, TingTing Hwang. 1-6 [doi]
• Power-Efficient and Programmable Hashing Accelerator for Massive Message ProcessingThi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima. 1-6 [doi]
• Approximate Accelerators: A Case Study using Runtime Reconfigurable ProcessorsFabian Lesniak, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• An 8-point Approximate DCT Design with Optimized Signed Digit EncodingZekun Wang, Shinichi Nishizawa, Shinji Kimura. 1-6 [doi]
• A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator DesignTai-Feng Chen, Yutaka Masuda, Tohru Ishihara. 1-6 [doi]
• Spiking Neural Networks Design-Space Exploration Platform Supporting Online and Offline LearningMoamen El-Masry, Sohaib Anees, Robert Weigel. 1-5 [doi]
• High Precision Winner-Take-All Circuit for Neural NetworksBijay Raj Paudel, Haibo Wang 0005, Spyros Tragoudas, Omkar Rijal. 1-6 [doi]
• Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable ReductionXinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura. 1-6 [doi]
• DE-C3: Dynamic Energy-Aware Compression for Computing-In-Memory-Based Convolutional Neural Network AccelerationGuan-Wei Wu, Cheng-Yang Chang, An-Yeu Andy Wu. 1-6 [doi]
• An Automotive Vision SoC Platform from IVI to AD Level 4Kevin Wohnrade, Darius Grantz, Martin Zeller, Jens Benndorf. 1-2 [doi]
• An Efficient Hardware Design for Fast Implementation of HQCChen Li, Suwen Song, Jing Tian 0004, Zhongfeng Wang 0001, Çetin Kaya Koç. 1-6 [doi]
• AC-Logic Family for Smart Dust and IoT ApplicationsHamza Saleem, Lubna Shah, Abdur Rehman, Hassan Saif, Rashad Ramzan. 1-5 [doi]
• A Comparative Analysis of Security Patterns for Enhancing Security in Safety-Critical SystemsSena Busra Yengec Tasdemir, Fahad Siddiqui 0001, Sakir Sezer, Henry Hui, Kieran McLaughlin, Balmukund Sonigara. 1-6 [doi]
• An optically reconfigurable gate array VLSI driven by an unstabilized power supply unitMasashi Tsujino, Minoru Watanabe, Nobuya Watanabe. 1-5 [doi]
• DEA-NIMC: Dynamic Energy-Aware Policy for Near/In-Memory Computing Hybrid ArchitectureYu-Cheng Wu, Chi-Tse Huang, An-Yeu Andy Wu. 1-6 [doi]
• Experience Migrating OpenCL to SYCL: A Case Study on Searches for Potential Off-Target Sites of Cas9 RNA-Guided Endonucleases on AMD GPUsZheming Jin, Jeffrey S. Vetter. 1-6 [doi]
• Covert Communication Attacks in Chiplet-based 2.5-D Integration SystemsYerzhan Mustafa, Selçuk Köse. 1-5 [doi]
• A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State OutputYuta Yachi, Masashi Tawada, Nozomu Togawa. 1-6 [doi]
• An Enhanced 1440 Coupled CMOS Oscillator Network to Solve Combinatorial Optimization ProblemsMarkus Graber, Klaus Hofmann. 1-6 [doi]
• Towards Hardware-Software Self-Adaptive Acceleration of Spiking Neural Networks on Reconfigurable Digital HardwareBrian Pachideh, Christian Zielke, Sven Nitzsche, Jürgen Becker 0001. 1-6 [doi]
• Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock NetworksAndres Ayes, Eby G. Friedman. 1-5 [doi]
• Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural NetworksMingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura. 1-6 [doi]
• P* Admissible Thermal-Aware Matrix Floorplanner for 3D ICsDima Al Saleh, Yousef Safari, Fahad Rahman Amik, Boris Vaisband. 1-6 [doi]
• Quadrature RF-Only Logic Family for Single-Chip Self-Powered TransceiversRashad Ramzan, Azam Beg, Syed Arsalan Jawed, Muhammad Aaquib Shahbaz, Muhammad Junaid. 1-5 [doi]
• LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V CoresYimin Gao, Sergiu Mosanu, Mohammad Nazmus Sakib, Vaibhav Verma, Xinfei Guo, Mircea Stan. 1-6 [doi]
• FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D IntegrationMadhava Sarma Vemuri, Umamaheswara Rao Tida. 1-6 [doi]
• An Investigation of Machine Learning Algorithms for High-bandwidth SQL Injection Detection Utilising BlueField-3 DPU TechnologyKasim Tasdemir, Rafiullah Khan, Fahad Siddiqui 0001, Sakir Sezer, Fatih Kurugollu, Alperen Bolat. 1-6 [doi]
• European Processor Initiative Demonstration of Integrated Semi-Autonomous Driving SystemDaniel Hofman, M. Brcic, Mario Kovac, Tim Hotfilter, Jürgen Becker 0001, Dominik Reinhardt, S. M. Grigorescu, R. Stevens, T. T. Vo. 1-6 [doi]
• HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space ExplorationJyun-Siou Huang, Ting-Han Chou, Juin-Ming Lu, Chih-Tsun Huang, Jing-Jia Liou. 1-6 [doi]
• Hardware Specification Aware Timing Side Channel Security AnalysisPrabuddha Chakraborty, Tasneem Suha, Swarup Bhunia. 1-6 [doi]
• BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoTMohamed El-Hadedy 0001, Russell Hua, Shahzman Saqib, Kazutomo Yoshii, Wen-mei Hwu, Martin Margala. 1-6 [doi]
• VLFF - A Very Low-power Flip-flop with only Two Clock TransistorsYugal Maheshwari, Manoj Sachdev. 1-6 [doi]
• Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory ComputingReon Oshio, Takumi Kuwahara, Mutsumi Kimura, Yasuhiko Nakashima. 1-6 [doi]
• Approximate Logarithmic Multipliers Using Half Compensation with Two Line SegmentsRenya Makimoto, Takashi Imagawa, Hiroyuki Ochi. 1-6 [doi]
• Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew SchedulingJaewan Yang, Taewhan Kim. 1-6 [doi]
• μThingNet: Leveraging Fine-Grained Power Analysis towards A Robust Zero-Day DefenderZhuoran Li, Dan Zhao 0001. 1-6 [doi]
• A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error RecoveryRenrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura. 1-6 [doi]
• ZodiacMSM: A Heterogeneous, Multi-node and Scalable Multi-Scalar Multiplication System for Zero Knowledge Proof AccelerationYiyang Xu, Dahong Qian. 1-6 [doi]
• A Non-deterministic Training Approach for Memory-Efficient Stochastic Neural NetworksBabak Golbabaei, Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima. 1-6 [doi]