Table of Contents

• High Sensitivity and Power Efficient Heater Structure for Bulk Micromachined Thermal AccelerometerRahul Mukherjee, Joydeep Basu, Prasanta Kumar Guha. 1-4 [doi]
• Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysisKaushal Kumari Neeraj, Nihar Ranjan Mohapatra. 1-4 [doi]
• Quantum Circuit Design of RECTANGLE Lightweight CipherP. Saravanan, J. Jenitha, S. R. Aasish, S. Sanjana. 1-4 [doi]
• A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGAAbi K. Krishnan, M. H. Supriya, Nalesh Sivanandan. 1-6 [doi]
• A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage AssessmentVenkata Reddy Kolagatla, J. Mervin, Shabbir Darbar, David Selvakumar, Sankha Saha. 1-5 [doi]
• Dual Stage Encoding Technique to Minimize Cross Coupling across NoC LinksS. Sharon Dev, S. M. Krishna, S. S. Archana, Rose George Kunthara, K. Neethu, Rekha K. James. 1-6 [doi]
• Formal Verification and Analysis of a Pseudo Random Number GeneratorDavid Selvakumar, J. Mervin, Shashikala Gunderao Pattanshetty, Vivian Desalphine. 1-6 [doi]
• Performance Comparison of Single Level STT and SOT MRAM Cells for Cache ApplicationsAshish Sura, Vikas Nehra. 1-4 [doi]
• Design and Implementation of Optimized Register File for Streaming ApplicationsAyazulla Khan Patan, Dimitrios Stathis 0001, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani. 1-4 [doi]
• FPGA based High Frequency Clock Phase Difference Measurement and CorrectionGanesh Mulay, Himanshu Patel, Manish Kumar, Kiral Ghodadra. 1-4 [doi]
• A Hardware Generator for Posit Arithmetic and its FPGA PrototypingDiksha Shekhawat, Apoorva Jangir, Jai Gopal Pandey. 1-6 [doi]
• FPGA Implementation of Different Stochastic Biochemical Reactions Involved in a CellSoma Barman Mandal, Moumita Acharya, Samik Basu 0003, Amlan Chakrabarti. 1-4 [doi]
• An All-CMOS Supply, Temperature and Process Invariant Hybrid Current Reference For Power Efficient IoT ApplicationsSoumya Tapse, Srivatsava Jandhyala, Adithya Reddy Banti. 1-4 [doi]
• A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT GenerationT. R. Varun, Rajasekhar Nagulapalli, Immanuel Raja. 1-4 [doi]
• Design of Energy-Efficient TSPC based D Flip-flop for CNTFET TechnologyK. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi. 1-4 [doi]
• Modeling of Thermal Properties of Semiconducting Monolayer MoSe2 and WSe2Yuvam Bhateja, Joshua Roy Palathinkal, Tamajeet Mandal, Pronay Roy, Dipankar Saha. 1-6 [doi]
• Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory ComputationMythrai, Pragna, Kavitha S, P. Singh, A. P. Shah, S. K. Vishwakarma, B. S. Reniwal. 1-4 [doi]
• Comprehensive Study and Photovoltaic Performance Analysis of Eco-friendly Perovskite Solar CellShubham, Chetan Pathak, Saurabh Kumar Pandey. 1-5 [doi]
• Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit DesignYatin Kumar Gupta, Yash Agrawal, Rutu Parekh, Bakul Gohel. 1-4 [doi]
• Broadband CMOS RF Logarithmic Power Detector for sub-6 GHz 5G ApplicationsSaurabh Katre, Shubham Tirmanwar, Debapratim Ghosh. 1-4 [doi]
• Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired ComputingSahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das. 1-4 [doi]
• Area-Time Scalable High Radix Montgomery Modular Multiplier for Large ModulusVenkata Reddy Kolagatla, Vivian Desalphine, David Selvakumar. 1-4 [doi]
• On Disabling Prefetcher to Amplify Cache Side ChannelsNirmal Kumar Boran, Kenrick Pinto, Bernard Menezes. 1-6 [doi]
• Radiation Hardened Area-Efficient 10T SRAM Cell for Space ApplicationsSayeed Ahmad, Naushad Alam, Mohd. Hasan. 1-6 [doi]
• High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM NetworkTresa Joseph, T. S. Bindiya. 1-4 [doi]
• LightFPGA: Scalable and Automated FPGA Acceleration of LightGBM for Machine Learning ApplicationsAlish Kanani, Swar Vaidya, Harshit Agarwal. 1-6 [doi]
• Automated Design of Analog Circuits using Machine Learning TechniquesS. Devi, Gourav Tilwankar, Rajesh Zele. 1-6 [doi]
• Process Development for Very Deep Etching of Silicon Using Two Layer Masks for Fabrication of Mechanically Decoupled MEMS GyroscopeDeepak K. Sharma, J. John, G. Supriya, Ashwini Jambhalikar, M. S. Giridhar. 1-4 [doi]
• Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage DomainSarita Yadav, Nitanshu Chauhan, Archana Pandey, Rajendra Pratap, Anand Bulusu. 1-5 [doi]
• A Multi-Octave Frequency Range SerDes with a DLL Free ReceiverRaman Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta. 1-6 [doi]
• Hardware Acceleration of SpMV Multiplier for Deep LearningMahesh Mahadurkar, Nalesh Sivanandan, S. Kala. 1-6 [doi]
• CNTFET Based Low Power Repeaters for On-Chip Interconnect SystemTakshashila Pathade, Yash Agrawal, Rutu Parekh, Girish Kumar Mekala. 1-4 [doi]
• Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed ApplicationsJay Pathak, Anand D. Darji. 1-4 [doi]