Table of Contents

• Look before you leap: An Access-based Prudent Page Migration for Hybrid MemoriesAishwarya Gupta, N. S. Aswathy, Hemangee K. Kapoor. 1-6 [doi]
• Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G ApplicationsShahid Jamil, Muhammad Usman, Muhammad Jawad Shakil, Jafar Hussain, Rashad Ramzan. 1-6 [doi]
• A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck ConverterMuhammad Jawad Shakil, Uzair Ahmed, Jafar Hussain, Hassan Saif, Rashad Ramzan. 1-6 [doi]
• REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot RemovalRafael Medina, Darong Huang, Giovanni Ansaloni, Marina Zapater, David Atienza. 1-6 [doi]
• Optimizing Constrained-Modulus Barrett Multiplier for Power and FlexibilityDeepraj Soni, Mohammed Nabeel 0001, Ramesh Karri, Michail Maniatakos. 1-6 [doi]
• Mapping of CNNs on multi-core RRAM-based CIM architecturesRebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph. 1-6 [doi]
• Method for Data-Driven Pruning in Micropipeline CircuitsCristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet. 1-6 [doi]
• Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D IntegrationShubham Kumar, Paul R. Genssler, Somaya Mansour, Yogesh Singh Chauhan, Hussam Amrouch. 1-6 [doi]
• Memory-Based Computing for Energy-Efficient AI: Grand ChallengesForoozan Karimzadeh, Mohsen Imani, Bahar Asgari, Ningyuan Cao, Yingyan Lin, Yan Fang. 1-8 [doi]
• Hardware Security Analysis of Arbiters: Trojan Modeling and Formal VerificationHala Ibrahim, Haytham Azmi, M. Watheq El-Kharashi, Mona Safar. 1-6 [doi]
• PR-PUF: A Reconfigurable Strong RRAM PUFGokulnath Rajendran, Furqan Zahoor, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay. 1-6 [doi]
• Dynamic Scheduling for Event-Driven Embedded Industrial ApplicationsHossein Taji, Jose Miranda, Miguel Peón Quirós, Szabolcs Balási, David Atienza. 1-6 [doi]
• Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-ChipYiyang Yu, Atif Shamim. 1-5 [doi]
• 3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane InterconnectSolomon Michael Serunjogi, Mihai Sanduleanu. 1-4 [doi]
• TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysisEsha Sarkar, Constantine Doumanidis, Michail Maniatakos. 1-6 [doi]
• Synthesis of SFQ Circuits with Compound GatesRassul Bairamkulov, Alessandro Tempia Calvino, Giovanni De Micheli. 1-6 [doi]
• Dynamic Digital Circuit Locking (DDCL): A Shield against Static Analysis AttacksZiyang Ye, Makoto Ikeda. 1-6 [doi]
• Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUsRobert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 1-6 [doi]
• An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow AnalysisShan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang. 1-6 [doi]
• Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics ApplicationsSagheer Ahmed, Jayesh Ambulkar, Debabrata Mondal, Ambika Prasad Shah. 1-6 [doi]
• Noise modeling using look-up tables and DC measurements for cryogenic applicationsGiovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mikaël Cassé, Philippe Galy. 1-6 [doi]
• FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICsKlajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf. 1-6 [doi]
• A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation TestPaolo Bernardi, Giorgio Insinga, Nima Kolahimahmoudi. 1-6 [doi]
• FPGA-implementation techniques to efficiently test application readiness of mixed-signal productsGabriel Rutsch, Konrad Maier, Wolfgang Ecker. 1-6 [doi]
• Hardware Implementation and Evaluation of an Information Processing FactoryWalaa Amer, Mariam Rakka, Rachid Karami, Minjun Seo, Mazen A. R. Saghir, Rouwaida Kanj, Fadi J. Kurdahi. 1-6 [doi]
• A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector MultiplicationGrégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza. 1-6 [doi]
• A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory ComputingOmar Numan, Martin Andraud, Kari Halonen. 1-6 [doi]
• Reducing Depth of Quantum Adder using Ling StructureSiyi Wang, Anupam Chattopadhyay. 1-6 [doi]
• An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory AccessYi Chen, Jie Lou, Christian Lanius, Florian Freye, Johnson Loh, Tobias Gemmeke. 1-6 [doi]
• Integrated Dynamic Memory Manager for a RISC-V ProcessorChun-Jen Tsai, Chun Wei Chao, Sheng-Di Hong. 1-5 [doi]
• A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency SynthesizerJunjie Li, Youming Zhang, Yunqi Cao, Xusheng Tang, Fengyi Huang. 1-4 [doi]
• A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based AlgorithmsUmair F. Siddiqi, Gary William Grewal, Shawki Areibi. 1-6 [doi]
• On the Reliability of RRAM-Based Neural NetworksHassen Aziza, Cristian Zambelli, Said Hamdioui, Sumit Diware, Rajendra Bishnoi, Anteneh Gebregiorgis. 1-8 [doi]
• On Protecting IJTAG using an Inherently Secure SIBAnjum Riaz, Gaurav Kumar, Pardeep Kumar, Yamuna Prasad, Satyadev Ahlawat. 1-6 [doi]
• SoftFlow: Automated HW-SW Confidentiality Verification for Embedded ProcessorsLennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers. 1-6 [doi]
• Optimized Quantum Circuit Implementation of Payoff FunctionSejin Lim, Hyunjun Kim, Kyungbae Jang, Siyi Wang, Anubhab Baksi, Anupam Chattopadhyay, Hwajeong Seo. 1-6 [doi]
• FeFET based Logic-in-Memory design methodologies, tools and open challengesCédric Marchand 0002, Alban Nicolas, Paul-Antoine Matrangolo, David Navarro, Alberto Bosio, Ian O'Connor. 1-6 [doi]
• Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic EncryptionCan Ayduman, Emre Koçer, Selim Kirbiyik, Ahmet Can Mert, Erkay Savas. 1-7 [doi]
• Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching AccelerationHanning Chen, Yeseong Kim, Elaheh Sadredini, Saransh Gupta, Hugo Latapie, Mohsen Imani. 1-6 [doi]
• Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded SystemsJean-Philippe Noël, E. Valea, Laurent Grenouillet, B. Chapuis, C. Fisher, A. Recoquillay, Bastien Giraud. 1-6 [doi]
• A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and MorphologyDheemanth Joshi, Aniket Arun Gangotri, Sai Pranay Chennamsetti, Gautham Bolar, Ganesan Thiagarajan, Sanjeev Gurugopinath. 1-6 [doi]
• Zero-Trust Communication between ChipsKais Belwafi, Hamdan Alshamsi, Ashfaq Ahmed, Abdulhadi Shoufan. 1-5 [doi]
• Accelerating Large Kernel Convolutions with Nested Winograd TransformationJingbo Jiang, Xizi Chen, Chi-Ying Tsui. 1-6 [doi]
• Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology NodesShayesteh Masoumian, Roel Maes, Rui Wang, Karthik Keni Yerriswamy, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil. 1-6 [doi]
• Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and ImplementationRupesh Raj Karn, Kashif Nawaz, Ibrahim Abe M. Elfadel. 1-6 [doi]
• Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA AcceleratorsSafiullah Khan, Ayesha Khalid, Ciara Rafferty, Yasir Ali Shah, Máire O'Neill, Wai-Kong Lee, Seong Oun Hwang. 1-6 [doi]
• A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol ConversionSuman Deb, Anupam Chattopadhyay, Avi Mendelson. 1-6 [doi]
• A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold ContactAnkit Sirohi, Jawar Singh. 1-6 [doi]
• Reconfigurable Rectifier for RF Energy Harvesting System at WiFi-6 Frequency Band for 2.5 VMouli Venkata Prakash Pittala, Aditya Kalyani, Nagaveni S. 1-6 [doi]
• ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network InferenceImlijungla Longchar, Hemangee K. Kapoor. 1-6 [doi]
• Towards Robust Process Design Kits with a Scalable DevOps Quality Assurance PlatformA. Datsuk, P. Ostrovskyy, F. Vater, C. Wieden. 1-6 [doi]