Peter Lidén - researchr alias

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Viewing Publication 1 - 11 from 11

1996

A fault model for switch-level simulation of gate-to-drain shortsPeter Dahlgren, Peter Lidén. vts 1996: 414-421 [doi]

1995

A Switch-level Algorithm for Simulation of Transients in Combinational LogicPeter Dahlgren, Peter Lidén. ftcs 1995: 207-216

Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS CheckersPeter Lidén, Peter Dahlgren. iscas 1995: 2124-2127

Switch-level modeling of transistor-level stuck-at faultsPeter Lidén, Peter Dahlgren. vts 1995: 208-215 [doi]

Fault Simulation and Physical Fault Injection Applied to MOS Transistor NetworksPeter Lidén. PhD thesis, Chalmers University of Technology, Gothenburg, Sweden, 1995. [doi]

1994

Modeling of Intermediate Node States in switch-Level NetworksPeter Dahlgren, Peter Lidén. dac 1994: 722-727 [doi]

Using heavy-ion radiation to validate fault-handling mechanismsJohan Karlsson, Peter Lidén, Peter Dahlgren, Rolf Johansson, Ulf Gunneflo. micro, 14(1):8-23, 1994. [doi]

On Latching Probability of Particle Induced Transients in Combinational NetworksPeter Lidén, Peter Dahlgren, Rolf Johansson, Johan Karlsson. ftcs 1994: 340-349

1993

Efficient modeling of switch-level networks containing undetermined logic node statesPeter Dahlgren, Peter Lidén. iccad 1993: 746-752 [doi]

1992

Transistor Fault Coverage for Self-Testing CMOS CheckersPeter Lidén, Peter Dahlgren, Jan Torin. itc 1992: 476-485

1991

Two Fault Injection Techniques for Test of Fault Handling MechanismsJohan Karlsson, Ulf Gunneflo, Peter Lidén, Jan Torin. itc 1991: 140-149

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