Subodh Kumar Singhal - researchr alias

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Viewing Publication 1 - 10 from 10

2023

An area-delay efficient single-precision floating-point multiplier for VLSI systemsAnuradha, Sujit Kumar Patel, Subodh Kumar Singhal. mam, 98:104798, April 2023. [doi]

2021

Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applicationsSubodh Kumar Singhal, Sujit Kumar Patel, Anurag Mahajan, Gaurav Saxena. elektrik, 29(4):2012-2028, 2021. [doi]

2020

Area-delay and energy efficient multi-operand binary tree adderSujit Kumar Patel, Subodh Kumar Singhal. iet-cds, 14(5):586-593, 2020. [doi]

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix AdderSubodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena. jcsc, 29(12), 2020. [doi]

2016

Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR ChannelizerBasant Kumar Mohanty, Subodh Kumar Singhal. cssp, 35(8):2958-2971, 2016. [doi]

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmeticBasant Kumar Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal, M. N. S. Swamy. integration, 54:37-46, 2016. [doi]

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed ArithmeticSubodh Kumar Singhal, Basant Kumar Mohanty. jcsc, 25(7), 2016. [doi]

2012

Efficient architectures for VLSI implementation of 2-D discrete Hadamard transformBasant K. Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal. iscas 2012: 1480-1483 [doi]

2009

Design of 1.5 GHz Quasilumped Microstrip Highpass FilterDeepak Sharma, Subodh Kumar Singhal, Ram Mehar Singh Dhariwal. cicsyn 2009: 268-270 [doi]

Design of 1.3 GHz Microstrip Highpass Filter Using Optimum Distributed Short Circuited StubsSubodh Kumar Singhal, Deepak Sharma, Ram Mehar Singh Dhariwal. cicsyn 2009: 264-267 [doi]

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