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    Journal: VLSI Signal Processing

    Volume 10, Issue 3

    207 -- 223Liang-Fang Chao, Edwin Hsing-Mean Sha. Static scheduling for synthesis of DSP algorithms on various models
    225 -- 236Henry Y. H. Chuang, Ling Chen. VLSI architecture for fast 2D discrete orthonormal wavelet transform
    237 -- 260Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri. Area efficient computing structures for concurrent error detection in systolic arrays
    261 -- 273Mark J. Bentum, Martin M. Samsom, Cornelis H. Slump. A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme
    275 -- 293Liang-Gee Chen, Yeu-Shen Jehng, Tzi-Dar Chiueh. Pipeline interleaving design for FIR, IIR, and FFT array processors
    295 -- 310Lothar Thiele. Resource constrained scheduling of uniform algorithms

    Volume 10, Issue 2

    111 -- 126Prashanth Kuchibhotla, Bhaskar D. Rao. A methodology for fast scheduling of partitioned systolic algorithms
    127 -- 140Mohammad Eshghi, Joanne DeGroat. A parallel binary structured LMS algorithm for transversal adaptive filters
    141 -- 152Francisco Argüello, Emilio L. Zapata. Constant geometry split-radix algorithms
    153 -- 168Giuseppe Caire, Javier Ventura-Traveset, M. Hollreiser, Ezio Biglieri. Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers
    169 -- 179Ling Chen, Henry Y. H. Chuang. Designing systolic architectures for complete Euclidean distance transform
    181 -- 199Jingling Xue. Closed-form mapping conditions for the synthesis of linear processor arrays

    Volume 10, Issue 1

    5 -- 23M. Yan, John V. McCanny, Y. Hu. VLSI architectures for vector quantization
    25 -- 40Randy S. Roberts, Herschel H. Loomis Jr.. Parallel computation structures for a class of cyclic spectral analysis algorithms
    41 -- 52Farhad Fuad Islam, Keikichi Tamaru. High speed merged array multiplication
    53 -- 65D. E. Metafas, Constantinos E. Goutis. A floating-point advanced cordic processor
    67 -- 84Chung-Yu Wu, Ron-Yi Liu. CMOS current-mode implementation of spatiotemporal probabilistic neural networks for speech recognition
    85 -- 92Cheng-Wen Wu, Ming-Kwang Chang. Bit-level systolic arrays for finite-field multiplications
    93 -- 106A. S. de la Vega, Paulo S. R. Diniz, Antônio C. Mesquita, Andreas Antoniou. A modular distributed-arithmetic implementation of the inner product and its application to digital filters
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