Abstract is missing.
- Comparison of NULL Convention Booth2 MultipliersChristina Smith, Scott Smith. 3-9
- A Comparison of NMOS to PMOS Starved Buffer Implementations for the Delay Line in a PWM DC-DC ConvertersCalvin Chiem, Hussain Al-Asaad. 10-16
- Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital SystemsHussain Al-Asaad. 17-21
- Planning and Designing Model of the Synthesized Design MethodXiaopeng Li, Wei Sun, Hui Ma, Bangchun Wen. 22-25
- Application on Programming The PIC Controller For a Sensitive Motor SpeedNader Barsoum. 26-32
- The Design and Implementation of Partial Virtual Machine for Device Driver Fault IsolationByoung Hong Lim, Inhyuk Kim, Young Ik Eom. 33-39
- Evolving More Testable Digital Combinational CircuitsNahid Mirzaie, Seyyed Javad Seyyed Mahdavi, Karim Mohammadi. 40-45
- Real Time Redundancy Study of a Exponential Time Dependent ModelM. Sharifi, M. Hamedanian, M. Naghizadeh. 46-54
- A Low-Power, Pulsed Domino CMOS 64-bit AdderRichard Hobson. 55-60
- Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length IncreaseSavithra Eratne, Claudia Romo, Eugene John. 61-66
- Delay-Insensitive Cell MatrixScott Smith, David Roclin, Jia Di. 67-73
- System - Level Partitioning for Embedded Systems Design Using Population - Based Incremental LearningFreddy Bolanos, Jose Aedo, Fredy Rivera. 74-80
- Thread Control Mechanism for Multithreading ProcessorTakanori Matsuzaki, Nozomu Urashima, Makoto Amamiya. 81-87
- Built-In Self-Test Circuit Optimization for Embedded CoresSrinivasa Vemuru, Sravani Kristem, Mohammed Y. Niamat. 88-92
- A Pipelined Salsal20 Encryption Hardware AcceleratorDayah Iman, Nikrouz Faroughi. 93-97
- Performance Evaluation of Multimedia Extensions on Variable Many-Core ProcessorsJong Myon Kim, Yong-Min Kim, Cheol Hong Kim. 98-104
- Leakage and Access Time Tradeoffs for Cache in High Performance MicroprocessorsSavithra Eratne, Claudia Romo, Eugene John, Byeong Kil Lee. 105-108
- An O(n) Parallel Shortest Path Algorithm and Its Hardware ImplementationJaehwan John Lee, Xiang Xiao. 117-123
- A Dynamic ECC Scheme for Lengthening the Lifetime of Flash MemoryShen-Ming Chung, Shun-Chieh Lin, Yi-Chen Chung. 133-139
- Architectural Sensitivity Analysis on Network WorkloadsByeong Lee, Satish Raghunath, Eugene John. 140-145
- An Effective Replacement Policy Focusing on Lifetime of a Cache LineHiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo. 146-152
- A Cost-Effective TCP/IP Offload Accelerator Design for Network Interface ControllerKoji Hashimoto, Vasily G. Moshnyaga. 153-159
- Thermal-aware Duplicated Filter Cache for Improving Processor ReliabilityHong Jun Choi, Young-Jin Park, Seung Gu Kang, Cheol Hong Kim, Sung Woo Chung, Jong Myon Kim, Dongseop Kwon. 160-168
- Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoCHooman Jarollahi, Richard Hobson. 169-175
- A Survey of Nanotechnology Principles in Modern Computing ArchitecturesMary Mehrnoosh Eshaghian-Wilner, Adam LeWinter. 176-181
- Quantum-Dot Cellular Automata Implementation of FPGA Configurable Logic BlocksMohammed Y. Niamat, Tejas Raviraj, Sowmya Panuganti, Srinivasa Vemuru. 182-188
- Memory Design for Multimedia ApplicationsShereen Afifi, Ayman Wahba, Abd-Elmoneim Wahdan. 189-195
- Development of FPGA Chip for Laser- based Distance Measurer for Defense ApplicationsParamjit Kaur, Opinder Sharma, Gautham Thyagarajan. 196-199
- Improved Energy Monitoring and Prognostics of Servers via High-Accuracy Real-Time Synchronization of Internal Telemetry SignalsKenny C. Gross, Kalyan Vaidyanathan. 200