Abstract is missing.
- The role of photonics in future data centersAl Davis. 1-2 [doi]
- Ambipolar double-gate FETs for the design of compact logic structuresKotb Jabeur, Ian O'Connor, Nataliya Yakymets, Sébastien Le Beux. 3-8 [doi]
- Performance and energy models for memristor-based 1T1R RRAM cellMahmoud Zangeneh, Ajay Joshi. 9-14 [doi]
- Accelerating thermal simulations of 3D ICs with liquid cooling using neural networksAlessandro Vincenzi, Arvind Sridhar, Martino Ruggiero, David Atienza. 15-20 [doi]
- Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristicSadiq M. Sait, Abdalrahman M. Arafeh. 21-26 [doi]
- SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representationVaradaraj Kamath Nileshwar, Roman Lysecky. 27-32 [doi]
- NBTI mitigation in microprocessor designsSimone Corbetta, William Fornaciari. 33-38 [doi]
- A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logicMarco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy. 39-44 [doi]
- Efficient selection and analysis of critical-reliability paths and gatesJifeng Chen, Shuo Wang, Mohammad Tehranipoor. 45-50 [doi]
- Breaking the power delivery wall using voltage stackingKaushik Mazumdar, Mircea Stan. 51-54 [doi]
- An efficient CPI stack counter architecture for superscalar processorsOsman Allam, Stijn Eyerman, Lieven Eeckhout. 55-58 [doi]
- An optimized multicore cache coherence design for exploiting communication localityLibo Huang, Zhiying Wang, Nong Xiao. 59-62 [doi]
- Parallel pipelined FFT architectures with reduced number of delaysManohar Ayinala, Keshab K. Parhi. 63-66 [doi]
- Design of an RNS reverse converter for a new five-moduli special setPiotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava. 67-70 [doi]
- On the automatic synthesis of parallel SW from RTL models of hardware IPsAndrea Acquaviva, Nicola Bombieri, Franco Fummi, Sara Vinco. 71-74 [doi]
- Top-down-based symmetrical buffered clock routingJin-Tai Yan, Ming-Chien Huang, Zhi-Wei Chen. 75-78 [doi]
- Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesisKeisuke Inoue, Mineo Kaneko. 79-82 [doi]
- A fully integrated switched-capacitor DC-DC converter with dual output for low power applicationHeungJun Jeon, Yong-Bin Kim. 83-86 [doi]
- High-level modeling of power consumption in active linear analog circuitsLaurent Bousquet, Emmanuel Simeu. 87-90 [doi]
- A novel power-gating scheme utilizing data retentiveness on cachesKyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura. 91-94 [doi]
- A zero-overhead IC identification technique using clock sweeping and path delay analysisNicholas Tuzzio, Kan Xiao, Xuehui Zhang, Mohammad Tehranipoor. 95-98 [doi]
- RAPA: reliability-aware priority arbitration strategy for network on chipJiajia Jiao, Yuzhuo Fu. 99-102 [doi]
- A high-performance online assay interpreter for digital microfluidic biochipsDaniel Grissom, Philip Brisk. 103-106 [doi]
- Reliable logic mapping on Nano-PLA architecturesMasoud Zamani, Mehdi Baradaran Tahoori. 107-110 [doi]
- Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuitJing Yang, Yong-Bin Kim. 111-116 [doi]
- Synchronization scheme for brick-based rotary oscillator arraysYing Teng, Baris Taskin. 117-122 [doi]
- A low-power all-digital GFSK demodulator with robust clock data recoveryPengpeng Chen, Bo Zhao, Rong Luo, Huazhong Yang. 123-128 [doi]
- Link breaking methodology: mitigating noise within power networksRenatas Jakushokas, Eby G. Friedman. 129-134 [doi]
- Unifying functional and parametric timing verificationLuís Guerra e Silva. 135-140 [doi]
- New & improved models for SAT-based bi-decompositionHuan Chen 0001, João Marques-Silva. 141-146 [doi]
- Lithography-aware layout compactionCurtis Andrus, Matthew R. Guthaus. 147-152 [doi]
- A design approach dedicated to network-based and conflict-free parallel interleaversAroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin 0001. 153-158 [doi]
- Distributed sensor data processing for many-coresJia Zhao, Russell Tessier, Wayne Burleson. 159-164 [doi]
- CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless linksSujay Deb, Kevin Chang, Miralem Cosic, Amlan Ganguly, Partha Pratim Pande, Deuk Hyoun Heo, Benjamin Belzer. 165-170 [doi]
- Voltage island-driven power optimization for application specific network-on-chip designKan Wang, Sheqin Dong, Satoshi Goto. 171-176 [doi]
- Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCsDavid Brenner, Cory E. Merkel, Dhireesha Kudithipudi. 177-182 [doi]
- TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operationsShuo Wang, Mohammad Tehranipoor. 183-188 [doi]
- Lazy suspect-set computation: fault diagnosis for deep electrical bugsDipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov. 189-194 [doi]
- Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage referenceDominik Gruber, Timm Ostermann. 195-200 [doi]
- Input and transistor reordering for NBTI and HCI reduction in complex CMOS gatesSaman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori. 201-206 [doi]
- Memristor: the illusive deviceKhaled N. Salama. 207-208 [doi]
- InMnAs magnetoresistive spin-diode logicJoseph S. Friedman, Nikhil Rangaraju, Yehea I. Ismail, Bruce W. Wessels. 209-214 [doi]
- An efficient approach for designing and minimizing reversible programmable logic arraysSajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu. 215-220 [doi]
- Modeling a single electron turnstile in HSPICEFabrizio Lombardi, Wei Wei, Jie Han. 221-226 [doi]
- Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuitsArne Heittmann, Tobias G. Noll. 227-232 [doi]
- Stepwise sleep depth control for run-time leakage power savingSeidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura. 233-238 [doi]
- An efficient power estimation methodology for complex RISC processor-based platformsSanthosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser, Eric Senn, Smaïl Niar. 239-244 [doi]
- ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation cachesBojan Maric, Jaume Abella, Mateo Valero. 245-250 [doi]
- A low stand-by power start-up circuit for SMPS PWM controllerIn-Seok Jung, Yong-Bin Kim. 251-254 [doi]
- Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLLOleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Geng Zheng. 255-258 [doi]
- A denial-of-service resilient wireless NoC architectureAmlan Ganguly, Mohsin Yusuf Ahmed, Anuroop Vidapalapati. 259-262 [doi]
- Sustainable multi-core architecture with on-chip wireless linksJacob Murray, John Klingner, Partha Pratim Pande, Behrooz Shirazi. 263-266 [doi]
- SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cellsZhe Zhang, Michael A. Turi, José G. Delgado-Frias. 267-270 [doi]
- A novel hybrid FIFO asynchronous clock domain crossing interfacing methodZaid Al-bayati, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria. 271-274 [doi]
- Density-reduction-oriented layer assignment for rectangle escape routingJin-Tai Yan, Jun-Min Chung, Zhi-Wei Chen. 275-278 [doi]
- NBTI effects on tree-like clock distribution networksWei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino. 279-282 [doi]
- A framework for high-level synthesis of heterogeneous MP-SoCYouenn Corre, Jean-Philippe Diguet, Dominique Heller, Loïc Lagadec. 283-286 [doi]
- Memory-based computing for performance and energy improvement in multicore architecturesKamran Rahmani, Prabhat Mishra, Swarup Bhunia. 287-290 [doi]
- Share memory aware scheduler: balancing performance and fairnessXi Li, Gangyong Jia, Yun Chen, Zongwei Zhu, Xuehai Zhou. 291-294 [doi]
- Alleviating NBTI-induced failure in off-chip output driversBhavitavya Bhadviya, Ayan Mandal, Sunil P. Khatri. 295-298 [doi]
- Mitigating electromigration of power supply networks using bidirectional current stressJing Xie, Vijaykrishnan Narayanan, Yuan Xie. 299-302 [doi]
- Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usageMarzieh Morshedzadeh Morshedzadeh, Ali Jahanian. 303-306 [doi]
- A scalable threshold logic synthesis method using ZBDDsAshok Kumar Palaniswamy, Spyros Tragoudas. 307-310 [doi]
- A memristor-based TCAM (ternary content addressable memory) cell: design and evaluationPilin Junsangsri, Fabrizio Lombardi. 311-314 [doi]
- Extending symmetric variable-pair transitivities using state-space transformationsPeter M. Maurer. 315-320 [doi]
- Crosslink insertion for variation-driven clock network constructionFuqiang Qian, Haitong Tian, Evangeline F. Y. Young. 321-326 [doi]
- WRIP: logic restructuring techniques for wirelength-driven incremental placementXing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert. 327-332 [doi]
- STEP: a unified design methodology for secure test and IP core protectionPranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty. 333-338 [doi]
- Towards systolic hardware acceleration for local complexity analysis of massive genomic dataAgathoklis Papadopoulos, Vasilis J. Promponas, Theocharis Theocharides. 339-344 [doi]
- A dual-phase compression mechanism for hybrid DRAM/PCM main memory architecturesSeungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Jongman Kim. 345-350 [doi]
- Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design explorationGeng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov. 351-356 [doi]
- Efficient folded VLSI architectures for linear prediction error filtersSayed Ahmad Salehi, Rassoul Amirfattahi, Keshab K. Parhi. 357-362 [doi]
- Synergistic integration of code encryption and compression in embedded systemsKamran Rahmani, Hadi Hajimiri, Kartik Shrivastava, Prabhat Mishra. 363-368 [doi]