Abstract is missing.
- Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocksBart Vermeulen, Kees Goossens. 1-8 [doi]
- System level simulation guided approach to improve the efficacy of clock-gatingSumit Ahuja, Wei Zhang, Sandeep K. Shukla. 9-16 [doi]
- State space reductions for scalable verification of asynchronous designsHaiqiong Yao, Hao Zheng 0001, Chris J. Myers. 17-24 [doi]
- Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacksO. Sarbishei, Yu Pang, Katarzyna Radecka. 25-32 [doi]
- Retiming arithmetic datapaths using Timed Taylor Expansion DiagramsDaniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon. 33-39 [doi]
- HIFSuite: Tools for HDL code conversion and manipulationNicola Bombieri, Giuseppe Di Guglielmo, Luigi Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli. 40-41 [doi]
- Quick formal modeling of communication fabrics to enable verificationSatrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras. 42-49 [doi]
- An improvement in decomposed reachability analysis for symbolic model checkingNicholas Donataccio, Hao Zheng. 50-57 [doi]
- Semi-formal functional verification by EFSM traversing via NuSMVGiuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Stefano Soffia, Marco Roveri. 58-65 [doi]
- Clock domain verification challenges and scalable solutionsPranav Ashar. 66 [doi]
- Towards analyzing functional coverage in SystemC TLM property checkingHoang M. Le, Daniel Große, Rolf Drechsler. 67-74 [doi]
- Coverage metrics for verification of concurrent SystemC designs using mutation testingAlper Sen, Magdy S. Abadir. 75-81 [doi]
- Static analysis of deadends in SVA constraintsAshvin Dsouza. 82-89 [doi]
- A case study of Time-Multiplexed Assertion Checking for post-silicon debuggingMing Gao, Kwang-Ting Cheng. 90-96 [doi]
- Fast and accurate UML State Chart modeling using TLM:::+::: control flow abstractionRainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker. 97-102 [doi]
- Automatic generation of host-compiled timed TLMs for high level designSamar Abdi. 103-104 [doi]
- Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPsNicola Bombieri, Franco Fummi, Valerio Guarnieri. 105-112 [doi]
- Automated synthesis of EDACs for FLASH memories with user-selectable correction capabilityMaurizio Caramia, Michele Fabiano, Andrea Miele, Roberto Piazza, Paolo Prinetto. 113-120 [doi]
- Utility of transaction-level hardware models in refinement checkingYogesh S. Mahajan, Sharad Malik. 121-128 [doi]
- An ontology and constraint based approach to cache preloadingRajiv Bhatia, Eyal Bin, Eitan Marcus, Gil Shurek. 129-136 [doi]
- ESL flows are enabled by high-level synthesis with universalityRishiyur S. Nikhil. 137 [doi]
- The relationship of code coverage metrics on high-level and RTL codeJohn Sanguinetti, Eugene Zhang. 138-141 [doi]
- ESL design and multi-core validation using the System-on-Chip EnvironmentWeiwei Chen, Xu Han, Rainer Dömer. 142-147 [doi]
- Model reduction techniques for the formal verification of hardware dependent softwareWolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten. 148-153 [doi]
- Verification of real-time properties for Hardware-dependent SoftwareWolfgang Müller 0003, Marcio F. da S. Oliveira, Henning Zabel, Markus Becker. 154-159 [doi]