Abstract is missing.
- Variability in Advanced Nanometer Technologies: Challenges and SolutionsDavide Pandini. 2 [doi]
- Subthreshold Circuit Design for Ultra-Low-Power ApplicationsYusuf Leblebici. 3 [doi]
- SystemC AMS Extensions: New Language - New Methods - New ApplicationsMartin Barnasconi, Markus Damm, Karsten Einwich. 4 [doi]
- Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial CorrelationMohsen Raji, Behnam Ghavami, Hamid R. Zarandi, Hossein Pedram. 5-15 [doi]
- Interpreting SSTA Results with CorrelationZeqin Wu, Philippe Maurine, Nadine Azémard, Gille Ducharme. 16-25 [doi]
- Residue Arithmetic for Variation-Tolerant Design of Multiply-Add UnitsIoannis Kouretas, Vassilis Paliouras. 26-35 [doi]
- Exponent Monte Carlo for Quick Statistical Circuit SimulationPaul Zuber, Vladimir Matvejev, Philippe Roussel, Petr Dobrovolný, Miguel Miranda. 36-45 [doi]
- Clock Repeater Characterization for Jitter-Aware Clock Tree SynthesisMonica Figueiredo, Rui L. Aguiar. 46-55 [doi]
- A Hardware Implementation of the User-Centric Display Energy ManagementVasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu, Shuhei Higashi. 56-65 [doi]
- On-chip Thermal Modeling Based on SPICE SimulationWei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino. 66-75 [doi]
- Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating StructuresJavier Castro, Pilar Parra, Antonio J. Acosta. 76-85 [doi]
- Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-ChipIraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris. 86-95 [doi]
- Data-Driven Clock Gating for Digital FiltersAlberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino. 96-105 [doi]
- Power Management and Its Impact on Power Supply NoiseHoward Chen, Indira Nair. 106-115 [doi]
- Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor SystemsMuhammad Khurram Bhatti, Muhammad Farooq, Cécile Belleudy, Michel Auguin, Ons Mbarek. 116-126 [doi]
- Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT TechniqueChih-Hsiang Lin, James B. Kuo. 127-135 [doi]
- Crosstalk in High-Performance Asynchronous DesignsRitej Bachhawat, Pankaj Golani, Peter A. Beerel. 136-145 [doi]
- Modeling and Reducing EMI in GALS and Synchronous SystemsTomasz Król, Milos Krstic, Xin Fan, Eckhard Grass. 146-155 [doi]
- Low-Power Dual-Edge Triggered State Retention Scan Flip-FlopHossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi. 156-164 [doi]
- Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware PlatformsNikolaos Zompakis, Martin Trautmann, Alexandros Bartzas, Stylianos Mamagkakis, Dimitrios Soudris, Liesbet Van der Perre, Francky Catthoor. 165-174 [doi]
- Dynamic Data Type Optimization and Memory Assignment MethodologiesAlexandros Bartzas, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, Fragkiskos Ieromnimon, Nikolaos S. Voros. 175-185 [doi]
- Accelerating Embedded Software Power Profiling Using Run-Time Power EmulationChristian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, Josef Haid. 186-195 [doi]
- Write Invalidation Analysis in Chip MultiprocessorsNewsha Ardalani, Amirali Baniasadi. 196-205 [doi]
- Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual PlatformMarius Gligor, Nicolas Fournel, Frédéric Pétrot, Fabien Colas-Bigey, Anne-Marie Fouilliart, Philippe Teninge, Marcello Coppola. 206-215 [doi]
- BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power OptimisationTom English, Ka Lok Man, Emanuel M. Popovici. 216-226 [doi]
- Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware ClusteringGaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. 227-236 [doi]
- Low Energy Voltage Dithering in Dual ::::V::::::::::DD:::::: CircuitsThomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel. 237-246 [doi]
- Product On-Chip Process Compensation for Low Power and Yield EnhancementNabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels. 247-255 [doi]
- Low-Power Soft Error Hardened LatchHossein Karimiyan Alidash, Vojin G. Oklobdzija. 256-265 [doi]
- Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of VariabilitiesBettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard. 266-275 [doi]
- Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical ImplementationYuri Stepchenkov, Yuri Diachenko, Victor Zakharov, Yuri Rogdestvenski, Nikolai Morozov, Dmitri Stepchenkov. 276-285 [doi]
- The Magic Rule of Tiles: Virtual Delay InsensitivityDelong Shang, Fei Xia, Stanislavs Golubcovs, Alexandre Yakovlev. 286-296 [doi]
- Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic GatesSidinei Ghissoni, João Baptista dos Santos Martins, Ricardo Augusto da Luz Reis, José C. Monteiro. 297-306 [doi]
- A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija. 307-316 [doi]
- Routing Resistance Influence in Loading Effect on Leakage AnalysisPaulo F. Butzen, André Inácio Reis, Renato P. Ribas. 317-325 [doi]
- Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor NetworksNéstor Suárez, Gustavo Marrero Callicó, Roberto Sarmiento, Octavio Santana, Anteneh A. Abbo. 326-335 [doi]
- An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic ProcessMotoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara. 336-346 [doi]
- Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V::::::t:::::: Domain By Architectural FoldingJoachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall. 347-356 [doi]
- A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone AdderFabio Frustaci, Marco Lanuzza. 357-366 [doi]