Table of Contents

• T4A: System-on-chip design using Tri-gate technologyAndrew Marshall. [doi]
• T3A: Design and managements of multiprocessor systems-on-chipsÜmit Y. Ogras. [doi]
• Message from conference general chairKaijian Shi. [doi]
• T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challengesPartha Pratim Pande, Alireza Nojeh, André Ivanov. [doi]
• T3B: Recent advancements in fiber optic transmission enabled by highly integrated mixed signal SoC and advanced digital signal processingHan Sun. [doi]
• T2B: Carbon nanotubes and opportunities for wireless on-chip interconnectAlireza Nojeh, Partha Pratim Pande, André Ivanov. [doi]
• T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodologyWolfgang Kunz, Dominik Stoffel, Joakim Urdahl. [doi]
• T2A: Clock implementation: A question of timingGerard M. Blair. [doi]
• T2B: Carbon nanotubes and opportunities for wireless on-chip interconnectAlireza Nojeh, Partha Pratim Pande, André Ivanov. [doi]
• T1A: Opportunities and challenges for secure hardware and verifying trust in integrated circuitsMohammad Tehranipoor, Charles Knapp. [doi]
• Message from program chairsThomas Buechner, Danella Zhao. [doi]
• Keynote speaker: "The Internet of Every-Thing: EDA perspectives"Tom Beckley. 2 [doi]
• Plenary speaker: "SoCs for Mobile Applications: Systems from 0 MPH to over 100 MPH"Scott Runner. 3 [doi]
• Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDesAshok Jaiswal, Dominik walk, Yuan Fang, Klaus Hofmann. 5-10 [doi]
• A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAMPeter Gadfort, Aravind Dasu, Ali Akoglu, Yoon Kah Leow, Michael Fritze. 11-16 [doi]
• Variation-aware Flip-Flop energy optimization for ultra low voltage operationTatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera. 17-22 [doi]
• Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operationNahid M. Hossain, Md Belayat Hossain, Masud H. Chowdhury. 24-28 [doi]
• CM_ISA++: An instruction set for dynamic task scheduling units for more than 1000 coresOliver Arnold, Benedikt Noethen, Gerhard Fettweis. 29-34 [doi]
• Power aware parallel computing on asymmetric multiprocessorSheheeda Manakkadu, Sourav Dutta, Nazeih M. Botros. 35-40 [doi]
• Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operationShinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera. 42-47 [doi]
• DESSERT: DESign Space ExploRation Tool based on power and energy at System-LevelSanthosh Kumar Rethinagiri, Oscar Palomar, Adrián Cristal, Osman S. Unsal, Michael M. Swift. 48-53 [doi]
• A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and belowWeiwei Shi, Oliver Chiu-sing Choy. 54-57 [doi]
• A CMOS self-powered monolithic light direction sensor with SAR ADCHongjiang Song, Zhijian Lu, Tao Luo, Jennifer Blain Christen, Hongyi Wang. 58-62 [doi]
• On wiring delays reduction of tree-based FPGA using 3-D fabricVinod Pangracious, Mohamed Sahbi Marrakchi, Habib Mehrez, Zied Marrakchi. 64-69 [doi]
• Adaptive multicast routing method for 3D mesh-based Networks-on-ChipPoona Bahrebar, Azarakhsh Jalalvand, Dirk Stroobandt. 70-75 [doi]
• Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) videoChih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang. 76-81 [doi]
• Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction techniqueJongyoon Hwang, Dongjoo Kim, Mun-Kyo Lee, Sun-Phil Nah, Minkyu Song. 83-87 [doi]
• Design of a low power CMOS 10bit flash-SAR ADCGi-Yoon Lee, Kwang Sub Yoon. 88-91 [doi]
• A systematic methodology to design high power terahertz and submillimeter-wave amplifiersSiavash Moghadami, Farzaneh JalaiBidgoli, Shahab Ardalan. 92-97 [doi]
• A clock generator based on multiplying delay-locked loopChorng-Sii Hwang, Ting-Li Chu, Wen-Cheng Chen. 98-102 [doi]
• A new design methodology for Voltage-to-Time Converters (VTCs) circuits suitable for Time-based Analog-to-Digital Converters (T-ADC)M. Wagih Ismail, Hassan Mostafa. 103-108 [doi]
• Reducing the turn-on time and overshoot voltage for a diode-triggered silicon-controlled rectifier during an electrostatic discharge eventAhmed Ginawi, Tian Xia, Robert Gauthier. 109-114 [doi]
• Electromyograph data acquisition and application using Cypress Programmable System on ChipShreeyash Salunke, Shreyas Darne, Keval Shah, Rishikesh Dhamapurkar. 115-118 [doi]
• Microcells for ICA-SOC for remote sensing of high energy radiationVijay K. Jain. 119-124 [doi]
• A low supply voltage mixed-signal maximum power point tracking controller for photovoltaic power systemJun-Hua Chiang, Bin-Da Liu, Shih-Ming Chen, Hong Tzer Yang. 125-129 [doi]
• Design and implementation of novel source synchronous interconnection in modern GPU chipsTao Li, Greg Sadowski. 130-135 [doi]
• PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systemsPei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang. 136-139 [doi]
• MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETsRamesh Nair, Ranga Vemuri. 140-145 [doi]
• Towards platform level power management in mobile systemsDavid Kadjo, Ümit Y. Ogras, Raid Ayoub, Michael Kishinevsky, Paul Gratz. 146-151 [doi]
• Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET)Azzedin D. Es-Sakhi, Masud H. Chowdhury. 152-155 [doi]
• Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET)Azzedin D. Es-Sakhi, Masud H. Chowdhury. 156-159 [doi]
• A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technologyChi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee. 160-164 [doi]
• Networks on chip design for real-time systemsAli Mahdoum. 165-170 [doi]
• Comparison between optimal interconnection network in different 2D and 3D NoC structuresFarzad Radfar, Masoud Zabihi, Reza Sarvari. 171-176 [doi]
• Flow control solution for efficient communication and congestion avoidance in NoCAhmed Aldammas, Adel Soudani, Abdullah Al-Dhelaan. 177-182 [doi]
• Run-time voltage detection circuit for 3-D IC power deliveryDivya Pathak, Ioannis Savidis. 183-187 [doi]
• Collision array based workload assignment for Network-on-Chip concurrencyHe Zhou, Linda S. Powers, Janet Roveda. 188-191 [doi]
• On circuit design of on-chip non-blocking interconnection networksYikun Jiang, Mei Yang. 192-197 [doi]
• Hardware architecture of an Internet Protocol Version 6 processorBoris Traskov, Ulrich Langenbach, Klaus Hofmann, Peter Gregorius. 198-203 [doi]
• Flexible reconfigurable architecture for DSP applicationsAbdulfattah Mohammad Obeid, Syed Manzoor Qasim, Mohammed S. BenSaleh, Zied Marrakchi, Habib Mehrez, Heni Ghariani, Mohamed Abid. 204-209 [doi]
• Very fast co-simulation model and accurate on-the-fly performance estimation methodology for heterogeneous MPSoCNicolas Serna, François Verdier. 210-215 [doi]
• Keynote speakerJ. Thomas Pawlowski. 217-218 [doi]
• Plenary speakerJeffrey D. Brown. 219 [doi]
• An all-digital on-chip abnormal temperature warning sensor for dynamic thermal managementChing-Che Chung, Jhih-Wei Li. 221-224 [doi]
• Time stretcher for a time-to-digital converter with a precisely matched current mirrorMuhammad Tanveer, Johan Borg, Jonny Johansson. 225-230 [doi]
• A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converterFang-Ting Chou, Zong-Yi Chen, Chung-Chih Hung. 231-235 [doi]
• An accelerated successive approximation technique for analog to digital converter designHaibo Wang, Ram Harshvardhan Radhakrishnan. 236-241 [doi]
• An energy efficient wireless Network-on-Chip using power-gated transceiversHemanta Kumar Mondal, Sujay Deb. 243-248 [doi]
• Heterogeneous photonic Network-on-Chip with dynamic bandwidth allocationAnkit Shah, Naseef Mansoor, Ben Johnstone, Amlan Ganguly, Sonia Lopez-Alarcon. 249-254 [doi]
• Benefits and costs of prediction based DVFS for NoCs at router levelCristinel Ababei, Nicholas Mastronarde. 255-260 [doi]
• Wiring resource minimization for physically-complex Network-on-Chip architecturesNickvash Kani, Azad Naeemi. 261-266 [doi]
• A framework for specifying, modeling, implementation and verification of SOC protocolsShahid Ikram, David Asher, Isam Akkawi, Jack Perveiler, Jim Ellis. 268-273 [doi]
• Reliability aware logic synthesis through rewritingSatish Grandhi, Christian Spagnol, Jiaoyan Chen, Emanuel M. Popovici, Sorin Cotafona. 274-279 [doi]
• Solar-supercapacitor harvesting system design for energy-aware applicationsMoeen Hassanalieragh, Tolga Soyata, Andrew Nadeau, Gaurav Sharma. 280-285 [doi]
• Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applicationsJyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu. 286-291 [doi]
• Evaluating mobile SOCs as an energy efficient DSP platformMatt Briggs, Payman Zarkesh-Ha. 293-298 [doi]
• New quantization error assessment methodology for fixed-point pipeline FFT processor designChen Yang, Yizhuang Xie, He Chen, Yi Deng. 299-305 [doi]
• Energy scalable approximate DCT architecture trading quality via boundary error-resiliencyBharat Garg, Nitesh K. Bharadwaj, G. K. Sharma. 306-311 [doi]
• Compensating imperfections in RF-DAC based transmitters using LUT-based predistortionBastian Mohr, Ye Zhang 0003, Jan Henning Mueller, Stefan Heinen. 312-316 [doi]
• Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designsHiroyuki Yamauchi, Worawit Somha. 318-323 [doi]
• Cost-optimal design of wireless pre-bonding test frameworkUnni Chandran, Dan Zhao. 324-329 [doi]
• IP watermark verification based on power consumption analysisCédric Marchand, Lilian Bossuet, Edward Jung. 330-335 [doi]
• A unique non-intrusive approach to non-ATE Based cul-de-sac SoC debugVasant Easwaran, Virendra Bansal, Greg Shurtz, Rahul Gulati, Mihir Mody, Prashant Karandikar, Prithvi Shankar. 336-339 [doi]
• REFLEX: Reconfigurable logic for entropy extractionVikram B. Suresh, Wayne P. Burleson. 341-346 [doi]
• 2 modulator with high-level sizing and power estimationAbhilash K. N, M. B. Srinivas. 347-352 [doi]
• A configurable packet classification architecture for Software-Defined NetworkingKeissy Guerra Perez, Xin Yang, Sandra Scott-Hayward, Sakir Sezer. 353-358 [doi]
• A stochastic learning algorithm for neuromemristive systemsCory E. Merkel, Dhireesha Kudithipudi. 359-364 [doi]
• Banquet speakerPaul Eremenko. 369 [doi]
• On designing circuit primitives for cortical processors with memristive hardwareDhireesha Kudithipudi, Cory E. Merkel, Yu Kee Ooi, Quitaba Saleh, Garrett S. Rose. 371-376 [doi]
• Emerging memristor technology enabled next generation cortical processorHai Li, Miao Hu, Xiaoxiao Liu, Mengjie Mao, Chuandong Li, Shukai Duan. 377-382 [doi]
• Memristor crossbar based multicore neuromorphic processorsTarek M. Taha, Raqibul Hasan, Chris Yakopcic. 383-389 [doi]
• Resistorless on-die high voltage power supply noise measurementRaj S. Dua, Siddharth Katare, Narayanan Natarajan. 390-392 [doi]
• Design of a low power multistandard transceiver chain based on current-reuse VCOYe Zhang 0003, Jan Henning Mueller, Muh-Dey Wei, Ralf Wunderlich, Stefan Heinen. 393-396 [doi]
• SoC Scan-Chain verification utilizing FPGA-based emulation platform and SCE-MI interfaceBill Jason Tomas, Yingtao Jiang, Mei Yang. 398-403 [doi]
• A new approach using symbolic analysis to compute path-dependent effective properties preserving hierarchySridhar Srinivasan, Ellis Cohen, Mark Hofmann. 404-408 [doi]
• A highly sensitive ISFET using pH-to-current conversion for real-time DNA sequencingMohammad M. Uzzal, Payman Zarkesh-Ha, Jeremy S. Edwards, Ezequiel Coelho, Priyanka Rawat. 410-414 [doi]
• A neural rehabilitation chip with neural recording, peak detection, spike rate counter, and biphasic neural stimulatorHongjiang Song, Chen Chen, Meng-Wei Lin, Kaijun Li, Jennifer Blain Christen. 415-419 [doi]
• High-frequency and power-efficiency ultrasound beam-forming processor for handheld applicationsGuo-Zua Wu, Song-Nien Tang, Chih-Chi Chang, Chien-Ju Lee, Kuan-Hsien Lin, Oscal T.-C. Chen. 420-424 [doi]
• A low complexity multi standard dual band CMOS polar transmitter for smart utility networksJan Henning Mueller, Ye Zhang 0003, Lei Liao, Aytac Atac, Zhimiao Chen, Bastian Mohr, Stefan Heinen. 426-430 [doi]
• A 25.5mW 10Gb/s inductorless receiver with an adaptive front-end in 0.13 µm CMOSSushrant Monga, Shouri Chatterjee. 431-436 [doi]
• A hardware acceleration scheme for memory-efficient flow processingXin Yang, Sakir Sezer, Shane O'Neill. 437-442 [doi]
• A body-bias based current sense amplifier for high-speed low-power embedded SRAMsTahseen Shakir, Manoj Sachdev. 444-448 [doi]
• Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspectiveHooman Farkhani, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi. 449-454 [doi]
• A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assistsChao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao. 455-462 [doi]