David Van Campenhout - researchr alias

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Viewing Publication 1 - 10 from 10

2003

Reasoning with Temporal Logic on Truncated PathsCindy Eisner, Dana Fisman, John Havlicek, Yoad Lustig, Anthony McIsaac, David Van Campenhout. cav 2003: 27-39 [doi]

The Definition of a Temporal Clock OperatorCindy Eisner, Dana Fisman, John Havlicek, Anthony McIsaac, David Van Campenhout. icalp 2003: 857-870 [doi]

2000

Collection and Analysis of Microprocessor Design ErrorsDavid Van Campenhout, Trevor N. Mudge, John P. Hayes. dt, 17(4):51-60, 2000. [doi]

1999

Functional design verification for microprocessors by error modelingDavid Van Campenhout. PhD thesis, University of Michigan, USA, 1999. [doi]

Timing verification of sequential dynamic circuitsDavid Van Campenhout, Trevor N. Mudge, Karem A. Sakallah. tcad, 18(5):645-658, 1999. [doi]

High-Level Test Generation for Design Verification of Pipelined MicroprocessorsDavid Van Campenhout, Trevor N. Mudge, John P. Hayes. dac 1999: 185-188 [doi]

1998

High-level design verification of microprocessors via error modelingDavid Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown. todaes, 3(4):581-599, 1998. [doi]

Specification and verification of pipelining in the ARM2 RISC microprocessorJames K. Huggins, David Van Campenhout. todaes, 3(4):563-580, 1998. [doi]

1996

Timing verification of sequential domino circuitsDavid Van Campenhout, Trevor N. Mudge, Karem A. Sakallah. iccad 1996: 127-132 [doi]

1993

Interactive Outlining: An Improved Approach Using Active ContoursDirk Daneels, David Van Campenhout, Wayne Niblack, William Equitz, Ron Barber, Erwin Bellon, Freddy Fierens. spieSR 1993: 226-233

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