Teodor Jové - researchr alias

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Viewing Publication 1 - 19 from 19

2018

2013

A review of the architecture of admission control schemes in the InternetLluís Fàbrega, Teodor Jové. npa, 5(3):1-32, 2013. [doi]

Network schemes for TCP elastic traffic in the InternetLluís Fàbrega, Teodor Jové. npa, 5(3):33-67, 2013. [doi]

Dynamic branch speculation in a speculative parallelization architecture for computer clustersJoan Puiggali, Boleslaw K. Szymanski, Teodor Jové, José-Luis Marzo. concurrency, 25(7):932-960, 2013. [doi]

2011

A network scheme for TCP elastic traffic with admission control using edge-to-edge per-aggregate measurements in class-based networksLluís Fàbrega, Teodor Jové, Pere Vilà, José-Luis Marzo. jhsn, 18(1):15-32, 2011. [doi]

2007

A guaranteed minimum throughput service for TCP flows using measurement-based admission controlLluís Fàbrega, Teodor Jové, Pere Vilà, José-Luis Marzo. ijcomsys, 20(1):43-63, 2007. [doi]

2006

Admission Control for TCP Flows Using Packet Classes and Edge-to-edge Measurements of AggregatesLluís Fàbrega, Teodor Jové, Pere Vilà, José-Luis Marzo, Liliana Carrillo. icc 2006: 760-765 [doi]

2005

A Packet Class-Based Scheme for Providing Throughput Guarantees to TCP FlowsLluís Fàbrega, Teodor Jové, Pere Vilà, José-Luis Marzo. ipom 2005: 76-87 [doi]

2003

Throughput guarantees for elastic flows using end-to-end admission controlLluís Fàbrega, Teodor Jové, Yezid Donoso Meisel. biosurveillance 2003: 153-162 [doi]

2002

A virtual network laboratory for learning IP networkingLluís Fàbrega, Jordi Massaguer, Teodor Jové, David Mérida. iticse 2002: 161-164 [doi]

2001

A Dynamic Multilevel MPLS Protection DomainEusebi Calle, Teodor Jové, Pere Vilà, José-Luis Marzo. drcn 2001: 289-294

1998

Qualitative Reasoning for Admission Control in ATM NetworksJosé-Luis Marzo, Antonio Bueno, Ramón Fabregat, Teodor Jové. ieaaie 1998: 387-398

1993

Multiprogrammation of parallel applications on the PAROS operating system kernelJesús Labarta, Judit Gimenez, Cristina Pujol, Teodor Jové. pdp 1993: 474-480 [doi]

1989

Reduced instruction buffer for RISC architecturesTeodor Jové, Jordi Cortadella. jsa, 27(1-5):87-93, 1989. [doi]

1988

Designing a branch target buffer for executing branches with zero time cost in a RISC processorJordi Cortadella, Teodor Jové. jsa, 24(1-5):573-580, 1988. [doi]

Dynamic RAM for on-chip instruction cachesJordi Cortadella, Teodor Jové. sigarch, 16(4):45-50, 1988. [doi]

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