Yasuhiro Takai - researchr alias

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Viewing Publication 1 - 6 from 6

2013

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits ConferenceMaurits Ortmanns, Timothy Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai. jssc, 48(1):3-7, 2013. [doi]

Session 17 overview: High-performance DRAM interfacesYasuhiro Takai, James Sung. isscc 2013: 304-305 [doi]

2005

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output bufferHiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi. jssc, 40(4):862-869, 2005. [doi]

2003

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output bufferTatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama. jssc, 38(5):762-768, 2003. [doi]

2000

1994

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architectureYasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe. jssc, 29(4):426-431, April 1994. [doi]

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