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Viewing Publication 1 - 100 from 440

2014

Early power-aware Design Space Exploration for embedded systems: MPEG-2 case studyFeriel Ben Abdallah, Chiraz Trabelsi, Rabie Ben Atitallah, Mourad Abed. issoc 2014: 1-8 [doi]

Adaptive runtime management of heterogenous MPSoCs: Analysis, acceleration and silicon prototypeOliver Arnold, Gerhard Fettweis. issoc 2014: 1-4 [doi]

L2_ISA++: Instruction set architecture extensions for 4G and LTE-advanced MPSoCsOliver Arnold, Felix Neumaerker, Gerhard Fettweis. issoc 2014: 1-8 [doi]

Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decodersMartin Broich, Tobias G. Noll. issoc 2014: 1-8 [doi]

System on chip design of a linear system solverJiri Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický. issoc 2014: 1-6 [doi]

Soft-core eFPGA for Smart Power applicationsMatteo Cuppini, Eleonora Franchi Scarselli, Claudio Mucci, Roberto Canegallo. issoc 2014: 1-4 [doi]

Keyed logic BIST for Trojan detection in SoCElena Dubrova, Mats Näslund, Gunnar Carlsson, Ben J. M. Smeets. issoc 2014: 1-4 [doi]

A transaction-level framework for design-space exploration of hardware-enhanced operating systemsDaniel Gregorek, Alberto García Ortiz. issoc 2014: 1-4 [doi]

Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systemsDaniel Günther, Andreas Bytyn, Rainer Leupers, Gerd Ascheid. issoc 2014: 1-7 [doi]

WOKE: A novel workflow model editorMikko Honkonen, Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen. issoc 2014: 1-8 [doi]

Constraint-driven frequency scaling in a Coarse Grain Reconfigurable ArrayWaqar Hussain, Henry Hoffmann, Tapani Ahonen, Jari Nurmi. issoc 2014: 1-6 [doi]

Gamification of System-on-Chip designTimo D. Hämäläinen, Erno Salminen. issoc 2014: 1-8 [doi]

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modelingJan Moritz Joseph, Thilo Pionteck. issoc 2014: 1-6 [doi]

A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCsChristoforos Kachris, Georgios Ch. Sirakoulis, Dimitrios Soudris. issoc 2014: 1-6 [doi]

A communication model and partitioning algorithm for streaming applications for an embedded MPSoCWayne Kelly, Martin Flasskamp, Gregor Sievers, Johannes Ax, Jianing Chen, Christian Klarhorst, Christoph Ragg, Thorsten Jungeblut, Andrew Sorensen. issoc 2014: 1-6 [doi]

I/O virtualization utilizing an efficient hardware system-level Memory Management UnitGeorge Kornaros, Konstantinos Harteros, Ioannis Christoforakis, Maria Astrinaki. issoc 2014: 1-4 [doi]

A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecturePei Liu, Ahmed Hemani, Kolin Paul. issoc 2014: 1-8 [doi]

Limits of gate-level power estimation considering real delay effects and glitchesMichael Meixner, Tobias G. Noll. issoc 2014: 1-7 [doi]

2014 International Symposium on System-on-Chip, SoC 2014, Tampere, Finland, October 28-29, 2014Jari Nurmi, Peeter Ellervee, Dragomir Milojevic, Ondrej Daniel, Tommi Paakki, editors, IEEE, 2014. [doi]

Fast Memory Region: 3D DRAM memory concept evaluated for JPEG2000 algorithmAlex Schönberger, Klaus Hofmann. issoc 2014: 1-4 [doi]

An implementation of Auto-Memoization mechanism on ARM-based superscalar processorYuuki Shibata, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima. issoc 2014: 1-8 [doi]

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gatingKimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura. issoc 2014: 1-7 [doi]

Implementation of Multicore communications APIJanne Virtanen, Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen. issoc 2014: 1-6 [doi]

Parallel and distributed simulation of networked multi-core systemsPhilipp Wehner, Diana Göhringer. issoc 2014: 1-5 [doi]

Formal verification of circuit-switched Network on chip (NoC) architectures using SPINAnam Zaman, Osman Hasan. issoc 2014: 1-8 [doi]

2013

2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013IEEE, 2013. [doi]

Evaluating the scalability of test busesAlexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski. issoc 2013: 1-6 [doi]

Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platformsMarco Balboni, Francisco Triviño, Jose Flich, Davide Bertozzi. issoc 2013: 1-6 [doi]

Efficient on-chip vector processing for multicore processorsSpiridon F. Beldianu, Sotirios G. Ziavras. issoc 2013: 1-4 [doi]

ViSA: A highly efficient slot architecture enabling multi-objective ASIP coresPeter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker. issoc 2013: 1-8 [doi]

Prefetching across a shared memory tree within a Network-on-Chip architectureJamie Garside, Neil C. Audsley. issoc 2013: 1-4 [doi]

Achieving QoS in NoC-based MPSoCs through Dynamic Frequency ScalingGuilherme Guindani, Fernando Gehm Moraes. issoc 2013: 1-6 [doi]

Implementation and evaluation of configuration scrubbing on CGRAs: A case studySyed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen. issoc 2013: 1-8 [doi]

Extending IP-XACT to embedded system HW/SW integrationAntti Kamppi, Lauri Matilainen, Joni-Matti Määttä, Erno Salminen, Timo D. Hämäläinen. issoc 2013: 1-8 [doi]

Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systemsChe-Chuan Kuo, Kun-Chih Chen, En-Jui Chang, An-Yeu Wu. issoc 2013: 1-4 [doi]

Framework for industrial embedded system product development and managementArttu Leppakoski, Erno Salminen, Timo D. Hämäläinen. issoc 2013: 1-6 [doi]

SW and HW speculative Nelder-Mead execution for high performance unconstrained optimizationArtur Mariano, Paulo Garcia, Tiago Gomes. issoc 2013: 1-5 [doi]

Dependency analysis and visualization tool for Kactus2 IP-XACT design frameworkJoni-Matti Määttä, Mikko Honkonen, Tommi Korhonen, Erno Salminen, Timo D. Hämäläinen. issoc 2013: 1-6 [doi]

A novel SAD architecture for variable block size motion estimation in HEVC video codingPurnachand Nalluri, Luis Nero Alves, Antonio Navarro. issoc 2013: 1-4 [doi]

On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCsBenedikt Noethen, Oliver Arnold, Gerhard Fettweis. issoc 2013: 1-7 [doi]

Split-cost communication model for improved MPSoC application mappingMaximilian Odendahl, Jerónimo Castrillon, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid. issoc 2013: 1-8 [doi]

TNODE: A low power sensor node processor for secure wireless networksGoran Panic, Oliver Schrape, Thomas Basmer, Frank Vater, Klaus Tittelbach-Helmrich. issoc 2013: 1-4 [doi]

Comparison of analog transactions using statisticsAlexander W. Rath, Volkan Esen, Wolfgang Ecker. issoc 2013: 1-6 [doi]

Adaptive QoS techniques for NoC-based MPSoCsMarcelo Ruaro, Everton Alceu Carara, Fernando Gehm Moraes. issoc 2013: 1-6 [doi]

Crosstalk avoidance coding for reliable data transmission of network on chipsZahra Shirmohammadi, Seyed Ghassem Miremadi. issoc 2013: 1-4 [doi]

FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compilerFlorian Stock, Andreas Koch 0001, Dietmar Hildenbrand. issoc 2013: 1-6 [doi]

Study of adaptive detection for MIMO-OFDM systemsEssi Suikkanen, Janne Janhunen, Shahriar Shahabuddin, Markku J. Juntti. issoc 2013: 1-4 [doi]

A cycle accurate simulation framework for asynchronous NoC designFederico Terraneo, Davide Zoni, William Fornaciari. issoc 2013: 1-8 [doi]

Partitioning constraints and signal routing approach for multi-FPGA prototyping platformMariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid. issoc 2013: 1-4 [doi]

A family of modular area- and energy-efficient QRD-accelerator architecturesUpasna Vishnoi, Tobias G. Noll. issoc 2013: 1-8 [doi]

Efficient distributed memory management in a multi-core H.264 decoder on FPGAJiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch. issoc 2013: 1-4 [doi]

Scheduling of parallelized synchronous dataflow actorsZheng Zhou, Karol Desnos, Maxime Pelcat, Jean-François Nezan, William Plishker, Shuvra S. Bhattacharyya. issoc 2013: 1-10 [doi]

System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systemsLorenzo Zuolo, Gabriele Miorandi, Cristian Zambelli, Piero Olivo, Davide Bertozzi. issoc 2013: 1-6 [doi]

2012

2012 International Symposium on System on Chip, ISSoC 2012, Tampere, Finland, October 10-12, 2012IEEE, 2012. [doi]

A double data rate 8T-cell SRAM architecture for systems-on-chipSaleh Abdel-Hafeez, Mohammad Shatnawi, Ann Gordon-Ross. issoc 2012: 1-4 [doi]

Improving logic-to-memory ratio in an embedded Multi-Processor system via code compressionRoberto Airoldi, Piia Saastamoinen, Jari Nurmi. issoc 2012: 1-4 [doi]

2 multi-standard turbo decoderRachid Al-Khayat, Amer Baghdadi, Michel Jézéquel. issoc 2012: 1-7 [doi]

Efficient VLSI architectures of QPP interleavers for LTE turbo decodersMartin Broich, Tobias G. Noll. issoc 2012: 1-6 [doi]

Instrumentation-driven model detection for dataflow graphsIlya Chukhman, William Plishker, Shuvra S. Bhattacharyya. issoc 2012: 1-8 [doi]

A flexible platform architecture for Gbps wireless communicationJeroen Declerck, Prabhat Avasare, Miguel Glassee, Amir Amin, Erik Umans, Andy Dewilde, Praveen Raghavan, Martin Palkovic. issoc 2012: 1-6 [doi]

Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCsLiang Guang, Ethiopia Nigussie, Juha Plosila, Jouni Isoaho, Hannu Tenhunen. issoc 2012: 1-7 [doi]

CRAVE: An advanced constrained random verification environment for SystemCFinn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler. issoc 2012: 1-7 [doi]

Tiny application-specific programmable processor for BCH decodingAnthony Van Herrewege, Ingrid Verbauwhede. issoc 2012: 1-4 [doi]

Effects of scaling a coarse-grain reconfigurable array on power and energy consumptionWaqar Hussain, Tapani Ahonen, Jari Nurmi. issoc 2012: 1-5 [doi]

A multi-banked shared-l1 cache architecture for tightly coupled processor clustersMohammad Reza Kakoee, Vladimir Petrovic, Luca Benini. issoc 2012: 1-5 [doi]

Hierarchical control flow matching for source-level simulation of embedded softwareKun Lu, Daniel Müller-Gritschneder, Ulf Schlichtmann. issoc 2012: 1-5 [doi]

Enhancing Cache Coherent Architectures with access patterns for embedded manycore systemsJussara Marandola, Stéphane Louise, Loïc Cudennec, Jean-Thomas Acquaviva, David A. Bader. issoc 2012: 1-7 [doi]

An automated framework for the simulation of mapping solutions on heterogeneous MPSoCsAntonio Miele, Christian Pilato, Donatella Sciuto. issoc 2012: 1-6 [doi]

Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCsLeandro Möller, Leandro Soares Indrusiak, Luciano Ost, Fernando Gehm Moraes, Manfred Glesner. issoc 2012: 1-4 [doi]

Scalability analysis of release and sequential consistency models in NoC based multicore systemsAbdul Naeem, Axel Jantsch, Zhonghai Lu. issoc 2012: 1-7 [doi]

Dataflow-based reconfigurable architecture for streaming applicationsAnja Niedermeier, Jan Kuper, Gerard J. M. Smit. issoc 2012: 1-4 [doi]

System-level software performance simulation considering out-of-order processor executionRoman Plyaskin, Thomas Wild, Andreas Herkersdorf. issoc 2012: 1-7 [doi]

Asynchronous parallel MPSoC simulation on the Single-Chip Cloud ComputerChristoph Roth, Simon Reder, Gokhan Erdogan, Oliver Sander, Gabriel Marchesan Almeida, Harald Bucher, Jürgen Becker. issoc 2012: 1-8 [doi]

Ultra-low latency NoC testing via pseudo-random test pattern compactionHervé Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik, Davide Bertozzi. issoc 2012: 1-6 [doi]

PowerMemo: A power profiling tool for mobile devices in an emulated wireless environmentShiao Li Tsao, Chih-Chen Kao, Ilter Suat, Yuchen Kuo, Yi-Hsin Chang, Cheng-Kun Yu. issoc 2012: 1-5 [doi]

A hybrid chip interconnection architecture with a global wireless network overlaid on top of a wired network-on-chipLing Wang, Zhen Wang, Yingtao Jiang. issoc 2012: 1-4 [doi]

Statistical timing characterizationZeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme. issoc 2012: 1-4 [doi]

Resource-shared custom instruction generation under performance/area constraintsDi Wu, Junwhan Ahn, Imyong Lee, Kiyoung Choi. issoc 2012: 1-6 [doi]

Application-aware spinlock control using a hardware scheduler in MPSoC platformsDiandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout. issoc 2012: 1-6 [doi]

Thermal/performance trade-off in network-on-chip architecturesDavide Zoni, Simone Corbetta, William Fornaciari. issoc 2012: 1-8 [doi]

2011

2011 International Symposium on System on Chip, SoC 2011, Tampere, Finland, October 31 - November 2, 2011IEEE, 2011. [doi]

A coarse-grained reconfigurable protocol processorMohammad Badawi, Ahmed Hemani. issoc 2011: 102-107 [doi]

OpenCL implementation of Cholesky matrix decompositionClaudio Brunelli, Eero Aho, Heikki Berg. issoc 2011: 62-67 [doi]

Bringing Network-on-Chip links to 45nmMarco Ferraresi, Giuseppina Gobbo, Daniele Ludovici, Davide Bertozzi. issoc 2011: 122-127 [doi]

Effects of loop unrolling and use of instruction buffer on processor energy consumptionVladimír Guzma, Teemu Pitkänen, Jarmo Takala. issoc 2011: 82-85 [doi]

Mismatch characterization of high-speed NoC links using asynchronous sub-samplingSebastian Höppner, Dennis Walter, Georg Ellguth, René Schüffny. issoc 2011: 112-115 [doi]

A hybrid model of speculative execution and scout threading for auto-memoization processorTomoki Ikegaya, Ryosuke Oda, Tatsuhiro Yamada, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima. issoc 2011: 22-28 [doi]

Customizable Datapath Integrated Lock UnitPekka Jääskeläinen, Erno Salminen, Otto Esko, Jarmo Takala. issoc 2011: 29-33 [doi]

Analyzing transport and MAC layer in system-level performance simulationSubayal Khan, Jukka Saastamoinen, Mikko Majanen, Jyrki Huusko, Jari Nurmi. issoc 2011: 1-8 [doi]

An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGASUli Kretzschmar, Armando Astarloa, Jusús Lazaro, Jaime Jimenez, Aitzol Zuloaga. issoc 2011: 96-101 [doi]

Synchronizing distributed state machines in a coarse grain reconfigurable architectureOmer Malik, Ahmed Hemani. issoc 2011: 128-135 [doi]

Static analysis method for deadlock detection in SystemC designsMikhail J. Moiseev, Alexey V. Zakharov, Ilya Klotchkov, Sergey I. Salishev. issoc 2011: 42-47 [doi]

Building a RTOS for MPSoC dataflow programmingYaset Oliva, Maxime Pelcat, Jean-François Nezan, Jean-Christophe Prévotet, Slaheddine Aridhi. issoc 2011: 143-146 [doi]

A set of traffic models for Network-on-Chip benchmarkingEsko Pekkarinen, Lasse Lehtonen, Erno Salminen, Timo D. Hämäläinen. issoc 2011: 78-81 [doi]

A system level power consumption estimation for MPSoCSanthosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser. issoc 2011: 56-61 [doi]

Applying IP-XACT in product data managementErno Salminen, Timo D. Hämäläinen, Marko Hännikäinen. issoc 2011: 86-91 [doi]

Increasing energy efficiency of automotive E/E-architectures with Intelligent Communication Controllers for FlexRayChristoph Schmutzler, Abdallah Lakhtel, Martin Simons, Jürgen Becker. issoc 2011: 92-95 [doi]

Automatic calibration of streaming applications for software mapping explorationWeihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid. issoc 2011: 136-142 [doi]

moviTest: A Test Environment dedicated to multi-core embedded architecturesTeodor Tite, Adelina Vig, Nicolae Olteanu, Cristian Cuna. issoc 2011: 108-111 [doi]

Impact of proactive temperature management on performance of Networks-on-ChipTim Wegner, Martin Gag, Dirk Timmermann. issoc 2011: 116-121 [doi]

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