Journal: IEEE Design & Test of Computers

Volume 10, Issue 2

2 -- 3. News
4 -- 5. Conference Reports
6 -- 12Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima. Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters
13 -- 23Samir Naik, Frank Agricola, Wojciech Maly. Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing
24 -- 33Robert P. Treuer, Vinod K. Agarwal. Built-In Self-Diagnosis for Repairable Embedded RAMs
34 -- 44Jos van Sas, Francky Catthoor, Hugo De Man. Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories
55 -- 0. 1994 Editorial Calendar
56 -- 68Steve Vinoski. RISE++: A Symbolic Environment for Scan-Based Testing
69 -- 77Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja. A Tutorial on Built-In Self-Test, Part 2: Applications
78 -- 90John W. Sheppard, William R. Simpson. Performing Effective Fault Isolation in Integrated Diagnostics
91 -- 0. New Products
92 -- 93. TTTC Newsletter
94 -- 95. DATC Newsletter