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    Journal: IEEE Design & Test of Computers

    Volume 10, Issue 4

    0 -- 0. Book Review
    4 -- 0. News
    7 -- 0Wayne Wei-Ming Dai, Kwang-Ting (Tim) Cheng. Guest Editor s Introduction
    8 -- 17Robert C. Frye, King L. Tai, Maureen Y. Lau, Thaddeus J. Gabara. Trends in Silicon-On-Silicon Multichip Modules
    18 -- 26David Staepelaere, Jeffrey Jue, Tal Dayan, Wayne Wei-Ming Dai. SURF: Rubber-Band Routing System for Multichip Modules
    27 -- 37Jun Dong Cho, Majid Sarrafzadeh, Mysore Sriram, Sung-Mo Kang. High-Performance MCM Routing
    38 -- 51Ting-Ting Y. Lin, Huoy-Yu Liou. A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy
    52 -- 63Hassan Rajaei, Rassul Ayani. Design Issues in Parallel Simulation Languages
    64 -- 75Rolf Ernst, Jörg Henkel, Thomas Benner. Hardware-Software Cosynthesis for Microcontrollers
    76 -- 82Fadi N. Sibai. A Fault-Tolerant Digital Artificial Neuron
    83 -- 87. 1993 Annual Index: Complete author and subject listing
    88 -- 90. New Products
    92 -- 0. DATC Newsletter
    93 -- 95. TTTC Newsletter

    Volume 10, Issue 3

    2 -- 0. Conference Reports
    4 -- 0. News
    5 -- 0Wayne Wolf. Guest Editor s Introduction: Hardware-Software Codesign
    6 -- 15Donald E. Thomas, Jay K. Adams, Herman Schmit. A Model and Methodology for Hardware-Software Codesign
    16 -- 28Asawaree Kalavade, Edward A. Lee. A Hardware-Software Codesign Methodology for DSP Applications
    29 -- 41Rajesh K. Gupta, Giovanni De Micheli. Hardware-Software Cosynthesis for Digital Systems
    42 -- 54Maximo H. Salinas, Barry W. Johnson, James H. Aylor. Implementation-Independent Model of an Instruction Set Architecture in VHDL
    56 -- 67Asim Smailagic, Daniel P. Siewiorek. A Case Study in Embedded-System Design: The VuMan 2 Wearable Computer
    68 -- 79Warren H. Debany Jr., Kevin A. Kwiat, Sami A. Al-Arian. A Method for Consistent Fault Coverage Reporting
    80 -- 86. A D&T Roundtable
    87 -- 91Franc Brglez. A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema?
    92 -- 0. New Products
    93 -- 0. DATC Newsletter
    94 -- 95. TTTC Newsletter

    Volume 10, Issue 2

    2 -- 3. News
    4 -- 5. Conference Reports
    6 -- 12Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima. Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters
    13 -- 23Samir Naik, Frank Agricola, Wojciech Maly. Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing
    24 -- 33Robert P. Treuer, Vinod K. Agarwal. Built-In Self-Diagnosis for Repairable Embedded RAMs
    34 -- 44Jos van Sas, Francky Catthoor, Hugo De Man. Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories
    55 -- 0. 1994 Editorial Calendar
    56 -- 68Steve Vinoski. RISE++: A Symbolic Environment for Scan-Based Testing
    69 -- 77Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja. A Tutorial on Built-In Self-Test, Part 2: Applications
    78 -- 90John W. Sheppard, William R. Simpson. Performing Effective Fault Isolation in Integrated Diagnostics
    91 -- 0. New Products
    92 -- 93. TTTC Newsletter
    94 -- 95. DATC Newsletter

    Volume 10, Issue 1

    2 -- 3. Conference Reports
    4 -- 5. Book Review
    6 -- 7Pinaki Mazumder, John P. Hayes. Guest Editor s Introduction: Testing and Improving the Testability of Multimegabit Memories
    8 -- 14A. J. van de Goor. Using March Tests to Test SRAMs
    15 -- 19Michihiro Inoue, Toshio Yamada, Atsushi Fujiwara. A New Testing Acceleration Chip for Low-Cost Memory Tests
    20 -- 28Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth. Generating Tests for Delay Faults in Nonscan Circuits
    30 -- 35Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri. Estimating the Complexity of Synthesized Designs from FSM Specifications
    36 -- 41B. Naveen, K. S. Raghunathan. An Automatic Netlist-to-Schematic Generator
    42 -- 51Peter C. Maxwell, Robert C. Aitken. Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
    52 -- 66William R. Simpson, John W. Sheppard. Fault Isolation in an Integrated Diagnostic Environment
    67 -- 72Karl R. Umstadter, Don L. Millard, Robert C. Block. Applications of a Laser-Induced Plasma Pathway to Testing of Electronic Modules
    73 -- 82Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja. A Tutorial on Built-in Self-Test. I. Principles
    83 -- 91. A D&T Roundtable
    92 -- 93. TTTC Newsletter
    94 -- 95. DATC Newsletter
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