| 0 | -- | 0 | Dilip K. Bhavsar, Yervant Zorian. ITC 97 Panel Sessions |
| 1 | -- | 0 | Yervant Zorian. D&T: 15th Year in Service |
| 4 | -- | 5 | . News |
| 6 | -- | 0 | Teruhiko Yamada. 1997 Asian Test Symposium |
| 8 | -- | 9 | Fabrizio Lombardi. Field-Programmable Gate Arrays |
| 10 | -- | 15 | Vaughn Betz, Jonathan Rose. How Much Logic Should Go in an FPGA Logic Block? |
| 16 | -- | 23 | Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, Weidong Xu, Paul M. Zavracky. Rothko: A Three-Dimensional FPGA |
| 24 | -- | 29 | Shanzhen Xing, William W. H. Yu. FPGA Adders: Performance Evaluation and Optimal Design |
| 30 | -- | 38 | Roger Woods, David W. Trainor, Jean-Paul Heron. Applying an XC6200 to Real-Time Image Processing |
| 39 | -- | 44 | Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara. Universal Fault Diagnosis for Lookup Table FPGAs |
| 45 | -- | 50 | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. Testing the Interconnect of RAM-Based FPGAs |
| 51 | -- | 62 | Kenneth L. Shepard, Vinod Narayanan. Conquering Noise in Deep-Submicron Digital ICs |
| 63 | -- | 70 | Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. Integrating Online and Offline Testing of a Switching Memory |
| 71 | -- | 82 | Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli. Scheduling for Embedded Real-Time Systems |
| 83 | -- | 90 | . A D&T Roundtable: Relative Effectiveness of Tests |
| 92 | -- | 94 | . Test Technology TC Newsletter |
| 95 | -- | 0 | . Design Automation TC Newsletter |
| 96 | -- | 0 | Hideo Fujiwara. Needed: Third-generation ATPG Benchmarks |