| 4 | -- | 5 | André Ivanov. Advances in 3-D Integrated Circuits, Systems, and CAD Tools |
| 6 | -- | 7 | Dae-Hyun Kim, Sung Kyu Lim. Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools |
| 8 | -- | 22 | Dae-Hyun Kim, Sung Kyu Lim. Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities |
| 23 | -- | 31 | Guruprasad Katti, S. W. Ho, Li Hong Yu, Songbai Zhang, Rahul Dutta, Roshan Weerasekera, Ka-Fai Chang, Jong-Kai Lin, Srinivasa Rao Vempati, Surya Bhattacharya. Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI) |
| 32 | -- | 39 | Yong Han, Boon Long Lau, Boo Yang Jung, Xiaowu Zhang. Heat Dissipation Capability of a Package-on-Package Embedded Wafer-Level Package |
| 40 | -- | 48 | Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen. A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers |
| 49 | -- | 58 | Dongjun Xu, Sai Manoj Sai Manoj P. D., Kanwen Wang, Hao Yu, Ningmei Yu, Mingbin Yu. A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller |
| 59 | -- | 70 | Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou. Hierarchical Test Integration Methodology for 3-D ICs |
| 71 | -- | 80 | Ishan G. Thakkar, Sudeep Pasricha. 3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization |
| 85 | -- | 86 | Theo Theocharides. Test Technology TC Newsletter |
| 88 | -- | 0 | Scott Davidson. A 3-D Forward into the Past |