External Links

    Journal: IEEE Design & Test of Computers

    Volume 8, Issue 1

    2 -- 5. News
    6 -- 13R. A. Sprague, K. J. Singh, R. T. Wood. Concurrent Engineering in Product Development
    14 -- 20Rolf Ernst, Jayaram Bhasker. Simulation-Based Verification for High-Level Synthesis
    21 -- 34Brion L. Keller, David P. Carlson, William Maloney. The Compiled Logic Simulator
    35 -- 42Wayne Wolf. Object Programming for CAD
    43 -- 49Raul Camposano, L. F. Saunders, R. M. Tabet. VHDL as Input for High-Level Synthesis
    50 -- 57Mehrdad Bidjan-Irani. A Rule-Based Design-for-Testability Rule Checker
    58 -- 66Vinod Chandra, M. R. Verma. A Fail-Safe Interlocking System for Railways
    67 -- 79Joachim Roos. Designing a Real-Time Coprocessor for Ada Tasking
    80 -- 90. A D&T Roundtable: ASIC Alternatives for System Design
    91 -- 93. TTTC Newsletter
    92 -- 93. Book Review
    94 -- 95. Conference Reports
    96 -- 97. Product Review
    102 -- 103. DATC Newsletter
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