Journal: IEEE Design & Test of Computers

Volume 8, Issue 4

2 -- 3. Editor-in-Chief s Message
4 -- 5. Disaster Recovery Centers
6 -- 17Karlheinz Hafner, Hartmut C. Ritter, Thomas M. Schwair, Stefan Wallstab, Michael Deppermann, Jürgen Gessner, Stefan Koesters, Wolf-Dietrich Moeller, Gerd Sandweg. Design and Test of an Integrated Cryptochip
18 -- 23David A. Fechser. A Methodology for Debugging ASIC Prototypes in the Field
25 -- 38John W. Sheppard, William R. Simpson. A Mathematical Model for Integrated Diagnostics
39 -- 51Jochen Kolzer, Johann Otto. Electrical Characterization of Megabit DRAMs, Part 2: Internal Testing
52 -- 62Richard Absher. Test Engineering Education is Rational, Feasible, and Relevant
64 -- 77I. D. Dear, Chryssa Dislis, Anthony P. Ambler, J. H. Dick. Economic Effects in Design and Test
82 -- 84. Book Review
84 -- 86. Conference Reports
87 -- 0. Direct Access Network
92 -- 93. TTTC Newsletter
94 -- 95. DATC Newsletter

Volume 8, Issue 3

12 -- 15Andrew J. Graham. The DAD Reamework Interactive
16 -- 30William R. Simpson, John W. Sheppard. System Complexity and Integrated Diagnostics
31 -- 35Paul S. Levy. Designing in Power-Down Test Circuits
36 -- 43G. Antonin, H.-D. Oberle, Jochen Kolzer. Electrical Characterization of Megabit DRAMs, Part 1: External Testing
44 -- 48Bjorn Dahlberg. Increasing Test Accuracy by Varying Driver Slew Rate
49 -- 57Rajiv Gupta, Rajagopalan Srinivasan, Melvin A. Breuer. Reorganizing Circuits to Aid Testability
58 -- 65Prawat Nagvajara, Mark G. Karpovsky, Lev B. Levitin. Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test
86 -- 0. Product Review
90 -- 91. Book Review
92 -- 93. TTTC Newsletter
94 -- 95. DATC Newsletter

Volume 8, Issue 2

2 -- 0. News
4 -- 10Stephen Walters. Computer-Aided Prototyping for ASIC-Based Systems
11 -- 25Richard I. Hartley, Kenneth Welles II, Michael Hartman, Abhijit Chatterjee, Paul Delano, Barbara Molnar, Colin Rafferty. A Rapid-Prototyping Environment for Digital-Signal Processors
27 -- 39David G. Boyer, Robert R. Cordell. Rapid Prototyping of High-Speed Communications Chips
40 -- 51Jan M. Rabaey, C. Chu, Phu Hoang, Miodrag Potkonjak. Fast Prototyping of Datapath-Intensive Architectures
52 -- 62Marc Engels, Rudy Lauwereins, J. A. Peperstraete. Rapid Prototyping for DSP Systems with Multiprocessors
63 -- 71Dilip K. Bhavsar. Testing Interconnections to Static RAMs
72 -- 86Elisabeth Auth, Michael H. Schulz. A Test-Pattern-Generation Algorithm for Sequential Circuits
88 -- 99. A D&T Roundtable- Six Sigma: Moving Towards Perfect Products
100 -- 102. Book Review
108 -- 109. DATC Newsletter
110 -- 111. TTTC Newsletter

Volume 8, Issue 1

2 -- 5. News
6 -- 13R. A. Sprague, K. J. Singh, R. T. Wood. Concurrent Engineering in Product Development
14 -- 20Rolf Ernst, Jayaram Bhasker. Simulation-Based Verification for High-Level Synthesis
21 -- 34Brion L. Keller, David P. Carlson, William Maloney. The Compiled Logic Simulator
35 -- 42Wayne Wolf. Object Programming for CAD
43 -- 49Raul Camposano, L. F. Saunders, R. M. Tabet. VHDL as Input for High-Level Synthesis
50 -- 57Mehrdad Bidjan-Irani. A Rule-Based Design-for-Testability Rule Checker
58 -- 66Vinod Chandra, M. R. Verma. A Fail-Safe Interlocking System for Railways
67 -- 79Joachim Roos. Designing a Real-Time Coprocessor for Ada Tasking
80 -- 90. A D&T Roundtable: ASIC Alternatives for System Design
91 -- 93. TTTC Newsletter
92 -- 93. Book Review
94 -- 95. Conference Reports
96 -- 97. Product Review
102 -- 103. DATC Newsletter