Journal: IBM Journal of Research and Development

Volume 24, Issue 6

660 -- 676Randolph G. Scarborough, Harwood G. Kolsky. Improved Optimization of FORTRAN Object Programs
677 -- 683Dennis Boyle, Paul Mundy, Thomas M. Spence. Optimization and Code Generation in a Compiler for Several Machines
684 -- 691Brian L. Marks. Compilation to Compact Code
692 -- 694John Cocke, Peter W. Markstein. Communication: Strenght Reduction for Division and Modulo with Application to Accessing a Multilevel Store
695 -- 715Frances E. Allen, J. Lawrence Carter, Janet Fabri, Jeanne Ferrante, William H. Harrison, Paul G. Loewner, Louise Trevillyan. The Experimental Compiling System
716 -- 731Juan M. Lafuente. Some Techniques for Compile-Time Analysis of User-Computer Interactions
732 -- 746Norbert J. Denil. A Business Language
747 -- 755Charles H. Sauer, Edward A. MacNair, Silvio Salza. A Language for Extended Queuing Network Models
756 -- 763Jose Luis Becerril, Jose Bondia, Ramón Casajuana, Francisco Valer. Grammar Characterization of Flowgraphs
764 -- 782David B. Lomet. A Data Definition Facility Based on a Value-Oriented Storage Model

Volume 24, Issue 5

530 -- 536Mihir Parikh, Donald E. Schreiber. Pattern Partitioning for Enhanced Proximity-Effect Corrections in Electron-Beam Lithography
537 -- 544W. D. Grobman, A. J. Speth, T. H. P. Chang. Proximity Correction Enhancements for 1-µm Dense Circuits
545 -- 553Donald E. Davis. Registration Mark Detection for Electron-Beam Lithography - EL1 System
554 -- 562J. H. Magerlein, D. J. Webb. Electron-Beam Resists for Lift-Off Processing with Potential Application to Josephson Integrated Circuits
563 -- 569Yonathan Bard. Estimation of State Probabilities Using the Maximum Entropy Principle
570 -- 581Philip Heidelberger. Variance Reduction Techniques for the Simulation of Markov Processes, I: Multiple Estimates
582 -- 597George Markowsky, Michael A. Wesley. Fleshing Out Wire Frames
598 -- 611J. S. Beeteson, K. T. Jarzebowski, B. R. Sowter. Digital System for Convergence of Three-Beam High-Resolution Color Data Displays
612 -- 621Bernard Vergnieres. Macro Generation Algorithms for LSI Custom Chip Design
622 -- 630Ho Chong Lee, Hi Dong Chai. Integral Point-Matching Method for Two-Dimensional Laplace Field Problems with Periodic Boundaries
631 -- 637Kurt E. Petersen. Silicon Torsional Scanning Mirror
638 -- 641Peter A. Franaszek. A General Method for Channel Coding

Volume 24, Issue 4

426 -- 437D. F. Kyser, R. Pyle. Computer Simulation of Electron-Beam Resist Profiles
438 -- 451Mihir Parikh. Proximity Effects in Electron Lithography: Magnitude and Correction Techniques
452 -- 460M. Hatzakis, B. J. Canavello, Jane M. Shaw. Single-Step Optical Lift-Off Process
461 -- 468H. R. Rottmann. Overlay in Lithography
469 -- 479Morris Shatzkes, Moshe Av-Ron, Robert A. Gdula. Defect-Related Breakdown and Conduction in SiO2
480 -- 485Wilm E. Donath. Stand-Alone Wiring Program for Josephson Logic
486 -- 495Shu Lin, Tadao Kasami, Saburo Yamamura. Existence of Good δ-Decodable Codes for the Two-User Multiple-Access Adder Channel
496 -- 511John S. Lew. Optimal Accelerometer Layouts for Data Recovery in Signature Verification
512 -- 517G. G. Adams. Procedures for the Study of the Flexible-Disk to Head Interface

Volume 24, Issue 3

267 -- 0S. S. Husson. Preface
268 -- 282Richard A. Larsen. A Silicon and Aluminum Dynamic Memory Technology
283 -- 290Kenneth S. Gray. Cross-Coupled Charge-Transfer Sense Amplifier and Latch Sense Scheme for High-Density FET Memories
291 -- 298B. F. Fitzgerald, E. P. Thoma. Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement
299 -- 309Ronald R. Troutman. VLSI Device Phenomena in Dynamic Memory and Their Application to Technology Development and Device Design
310 -- 317H. J. Geipel, W. K. Tice. Reduction of Leakage by Implantation Gettering in VLSI Circuits
318 -- 327T. C. Lo, R. E. Scheuerlein, R. Tamlyn. A 64K FET Dynamic Random Access Memory: Design Considerations and Description
328 -- 338A. Tzou, Y. Gopalakrishna, E. Blaser, O. Bar-Gadda, R. Carballo. A 256K-Bit Charge-Coupled Device Memory
339 -- 347V. Leo Rideout, John J. Walker, Alice Cramer. A One-Device Memory Cell Using a Single Layer of Polysilicon and a Self-Registering Metal-to-Polysilicon Contact
348 -- 352L. A. Kasprzak, A. K. Gaind. Near-Ideal Si-SiO2 Interfaces
353 -- 361D. W. Ormond, J. R. Gardiner. Reliability of SiO2 Gate Dielectric with Semi-Recessed Oxide Isolation
362 -- 369H. J. Geipel, R. B. Shasteen. Implanted Source/Drain Junctions for Polysilicon Gate Technologies
370 -- 377Roger L. Verkuil, Huntington W. Curtis, Mun S. Pak. A Contactless Method for High-Sensitivity Measurement of p-n Junction Leakage
378 -- 389A. Bhattacharyya, D. P. Gaffney, R. A. Kenyon, P. B. Mollier, J. E. Selleck, F. W. Wiedman. 1/N Circuit and Device Technology
390 -- 397Douglas C. Bossen, Mu Y. Hsiao. A System Solution to the Memory Soft Error Problem
398 -- 409Charles H. Stapper, A. N. McLaren, M. Dreckmann. Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product
410 -- 413I. T. Ho, J. Riseman, H. Greenhaus. A Charge Injection Transistor Memory Cell

Volume 24, Issue 2

107 -- 112Wilhelm Anacker. Josephson Computer Technology: An IBM Research Project
113 -- 129J. Matisoo. Overview of Josephson Technology Logic and Memory
130 -- 142T. R. Gheewala. Design of 2.5-Micrometer Josephson Current Injection Logic (CIL)
143 -- 154S. M. Faris, Walter H. Henkels, E. A. Valsamakis, H. H. Zappe. Basic Design of a Josephson Technology Cache Memory
155 -- 166P. Gueret, A. Moser, P. Wolf. Investigations for a Josephson Computer Main Memory with Single-Flux-Quantum Cells
167 -- 171Alan V. Brown. An Overview of Josephson Packaging
172 -- 177H. C. Jones, Dennis J. Herrell. The Characteristics of Chip-to-Chip Signal Propagation in a Package Suitable for Superconducting Circuits
178 -- 187R. F. Broom, W. Kotyczka, A. Moser. Modeling of Characteristics for Josephson Junctions Having Nonuniform Width or Josephson Current Density
188 -- 194Irving Ames. An Overview of Materials and Process Aspects of Josephson Integrated Circuit Fabrication
195 -- 205J. H. Greiner, Charles J. Kircher, S. P. Klepner, S. K. Lahiri, A. J. Warnecke, S. Basavaiah, E. T. Yen, John M. Baker, P. R. Brosious, H.-C. W. Huang, M. Murakami, Irving Ames. Fabrication Process for Josephson Integrated Circuits
206 -- 211R. F. Broom, R. Jaggi, Th. O. Mohr, A. Oosenbrug. Effect of Process Variables on Electrical Properties of Pb-Alloy Josephson Junctions
212 -- 222R. F. Broom, Robert B. Laibowitz, Th. O. Mohr, W. Walter. Fabrication and Properties of Niobium Josephson Tunnel Junctions
223 -- 234John M. Baker, Charles J. Kircher, J. W. Matthews. Structure of Tunnel Barrier Oxide for Pb-Alloy Josephson Junctions
235 -- 242Charles J. Kircher, S. K. Lahiri. Properties of AuIn2 Resistors for Josephson Integrated Circuits
243 -- 252Frank F. Tsui. JSP - A Research Signal Processor in Josephson Technology

Volume 24, Issue 1

2 -- 14Martin S. Schmokler. Design of Large ALUs Using Multiple PLA Macros
15 -- 22Edward B. Eichelberger, Eric Lindbloom. A Heuristic Test-Pattern Generator for Programmable Logic Arrays
23 -- 31Robert L. Golden, Patricia A. Latus, Paul Lowy. Design Automation and the Programmable Logic Array Macro
32 -- 42Arvind M. Patel. Error Recovery Scheme for the IBM 3850 Mass Storage System
43 -- 48Peter A. Franaszek. Synchronous Bounded Delay Coding for Input Restricted Channels
49 -- 55Vijay Ahuja. Determining Deadlock Exposure for a Class of Store and Forward Communication Networks
56 -- 63Shu Lin, George Markowsky. On a Class of One-Step Majority-Logic Decodable Cyclic Codes
64 -- 74Michael A. Wesley, Tomás Lozano-Pérez, Lawrence I. Lieberman, Mark A. Lavin, David D. Grossman. A Geometric Modeling System for Automated Mechanical Assembly
75 -- 84Kin-Man Chung, Fabrizio Luccio, Chak-Kuen Wong. On the Complexity of Permuting Records in Magnetic Bubble Memory Systems