921 | -- | 922 | Shoji Kawahito. Foreword |
923 | -- | 929 | Atsushi Iwata, Yoshitaka Murasaka, Tomoaki Maeda, Takafumi Ohmoto. Background Calibration Techniques for Low-Power and High-Speed Data Conversion |
930 | -- | 937 | Oren Eliezer, Robert B. Staszewski. Built-In Measurements in Low-Cost Digital-RF Transceivers |
938 | -- | 944 | Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai. 0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7 Current Efficiency in 65 nm CMOS |
945 | -- | 952 | Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura. An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O |
953 | -- | 959 | Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Takayasu Sakurai, Makoto Takamiya. A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57 Ripple Reduction at Low Output Voltage |
960 | -- | 967 | Indika U. K. Bogoda Appuhamylage, Shunsuke Okura, Toru Ido, Kenji Taniguchi. An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference |
968 | -- | 976 | Mengshu Huang, Leona Okamura, Tsutomu Yoshihara. An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non-volatile Memory |
977 | -- | 984 | Mohiuddin Hafiz, Shinichi Kubota, Nobuo Sasaki, Kentaro Kimoto, Takamaro Kikkawa. A 2 Gb/s 1.8 pJ/bit Differential BPSK UWB-IR Transmitter Using 65 nm CMOS Technology |
985 | -- | 991 | Lechang Liu, Takayasu Sakurai, Makoto Takamiya. 0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver |
992 | -- | 998 | Katsuyuki Ikeuchi, Hideki Kusamitsu, Mutsuo Daito, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai. 1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling |
999 | -- | 1007 | Hong Zhang, Xue Li, Suming Lai, Pinyi Ren. A High-Linearity 264-MHz Source-Follower-Based Low-Pass Filter with High-Q Second-Order Cell for MB-OFDM UWB |
1008 | -- | 1015 | Yuya Ono, Takuichi Hirano, Kenichi Okada, Jiro Hirokawa, Makoto Ando. Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate |
1016 | -- | 1023 | Takushi Hashida, Yuuki Araga, Makoto Nagata. A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength |
1024 | -- | 1031 | Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata. On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement |
1032 | -- | 1041 | Pravit Tongpoon, Fujihiko Matsumoto, Takeshi Ohbuchi, Hitoshi Takeuchi. A Differential Input/Output Linear MOS Transconductor |
1042 | -- | 1048 | Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa. Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit |
1049 | -- | 1052 | Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda. A 60-GHz Injection-Locked Frequency Divider Using Multi-Order ::::LC:::: Oscillator Topology for Wide Locking Range |
1053 | -- | 1056 | Shigeki Koya, Takashi Ogawa, Hiroyuki Takazawa, Akishige Nakajima, Shinya Osakabe, Yasushi Shigeno. Design and Performance of Intergate-Channel-Connected Multi-Gate pHEMT for Antenna Switch |
1057 | -- | 1060 | Ryo Minami, Jee Young Hong, Kenichi Okada, Akira Matsuzawa. Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip |
1061 | -- | 1064 | Tomohiko Ogawa, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Satoshi Ito, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu. Design for Testability That Reduces Linearity Testing Time of SAR ADCs |
1065 | -- | 1068 | Zule Xu, Jun Gyu Lee, Shoichi Masui. Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL |
1069 | -- | 1071 | Sang-hun Kim, Yong-Hwan Lee, Hoon-Ju Chung, Young-Chan Jang. A Bootstrapped Analog Switch with Constant On-Resistance |
1072 | -- | 1075 | Tadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai. Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout |
1076 | -- | 1083 | Xiaoshe Zhai, Yingsan Geng, Jianhua Wang, Guogang Zhang, Yan Wang. Modeling of the Electrical Fast Transient/Burst Generator and the Standard Injection Clamp |
1084 | -- | 1090 | Kenji Suzuki, Mamoru Ugajin, Mitsuru Harada. A 1-Mbps 1.6-µA Active-RFID CMOS LSI for the 300-MHz Frequency Band with an All-Digital RF Transmitting Scheme |
1091 | -- | 1097 | Tadashi Kido, Hiroyuki Deguchi, Mikio Tsuji. Compact Planar Bandpass Filters with Arbitrarily-Shaped Conductor Patches and Slots |
1098 | -- | 1104 | Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada. 1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells |
1105 | -- | 1111 | Mohammad Javad Sharifi. A Theoretical Study of the Performance of a Single-Electron Transistor Buffer |
1112 | -- | 1119 | Li-Rong Wang, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee. Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design |
1120 | -- | 1126 | Zunchao Li, Jinpeng Xu, Linlin Liu, Feng Liang, Kuizhi Mei. Analytical Drain Current Modeling of Dual-Material Surrounding-Gate MOSFETs |
1127 | -- | 1130 | Viet-Hoang Le, Hoai-Nam Nguyen, Sun-a Kim, Seok-Kyun Han, Sang-Gug Lee. A Wideband Noise Cancelling Low Noise Amplifier for 3GPP LTE Standard |
1131 | -- | 1134 | Hiroshi Hatano. A Fundamental Analysis of Single Event Effects on Clocked CVSL Circuits with Gated Feedback |
1135 | -- | 1137 | Kyung Won Lee, Ic-Pyo Hong, Yeong-Chul Chung, Jong Gwan Yook. Studies on a Fiber-Reinforced Ceramic Composite Layer for On-Board Antenna Protection |
1138 | -- | 1140 | Sungho Beck, Stephen T. Kim, Michael Lee, Kyutae Lim, Joy Laskar, Manos M. Tentzeris. A New Power-Consumption Optimization Technique for Two-Stage Operational Amplifiers |