External Links

    Journal: Integration

    Volume 7, Issue 3

    211 -- 0Lambert Spaanenburg. Editorial
    213 -- 230Reiner Kolla, Paul Molitor. A note on hierarchical layer-assignment
    231 -- 245Yue-Sun Kuo, T. C. Chern, Wei Kuan Shih. Fast algorithm for optimal layer assignment
    247 -- 266Jeffrey J. Joyce. Formal specification and verification of microprocessor systems
    267 -- 281Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri. Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach
    283 -- 302C. P. Ravikumar, Sarma Sastry. A hardware accelerator for hierarchical VLSI routing
    303 -- 324Alaaeldin A. M. Amin, Kent F. Smith. Test generation and fault detection for VLSI PPL circuits
    325 -- 0Sharad C. Seth, Vishwani D. Agrawal. A new model for computation of probabilistic testability in combinational circuits
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